qemu/include/hw/watchdog/wdt_aspeed.h
Andrew Jeffery f55d613bc9 watchdog: wdt_aspeed: Add support for the reset width register
The reset width register controls how the pulse on the SoC's WDTRST{1,2}
pins behaves. A pulse is emitted if the external reset bit is set in
WDT_CTRL. On the AST2500 WDT_RESET_WIDTH can consume magic bit patterns
to configure push-pull/open-drain and active-high/active-low
behaviours and thus needs some special handling in the write path.

As some of the capabilities depend on the SoC version a silicon-rev
property is introduced, which is used to guard version-specific
behaviour.

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-09-04 15:21:54 +01:00

35 lines
745 B
C

/*
* ASPEED Watchdog Controller
*
* Copyright (C) 2016-2017 IBM Corp.
*
* This code is licensed under the GPL version 2 or later. See the
* COPYING file in the top-level directory.
*/
#ifndef ASPEED_WDT_H
#define ASPEED_WDT_H
#include "hw/sysbus.h"
#define TYPE_ASPEED_WDT "aspeed.wdt"
#define ASPEED_WDT(obj) \
OBJECT_CHECK(AspeedWDTState, (obj), TYPE_ASPEED_WDT)
#define ASPEED_WDT_REGS_MAX (0x20 / 4)
typedef struct AspeedWDTState {
/*< private >*/
SysBusDevice parent_obj;
QEMUTimer *timer;
/*< public >*/
MemoryRegion iomem;
uint32_t regs[ASPEED_WDT_REGS_MAX];
uint32_t pclk_freq;
uint32_t silicon_rev;
uint32_t ext_pulse_width_mask;
} AspeedWDTState;
#endif /* ASPEED_WDT_H */