mirror of
https://gitlab.com/qemu-project/qemu
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aee7499a59
It uses a different capsbase and opregbase than the Xilinx device. Signed-off-by: Liming Wang <walimisdev@gmail.com> Signed-off-by: Andreas Färber <andreas.faerber@web.de> Cc: Igor Mitsyanko <i.mitsyanko@samsung.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
366 lines
11 KiB
C
366 lines
11 KiB
C
/*
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* QEMU USB EHCI Emulation
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or(at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_USB_EHCI_H
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#define HW_USB_EHCI_H 1
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#include "hw/hw.h"
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#include "qemu/timer.h"
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#include "hw/usb.h"
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#include "monitor/monitor.h"
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#include "trace.h"
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#include "sysemu/dma.h"
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#include "sysemu/sysemu.h"
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#include "hw/pci/pci.h"
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#include "hw/sysbus.h"
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#ifndef EHCI_DEBUG
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#define EHCI_DEBUG 0
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#endif
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#if EHCI_DEBUG
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#define DPRINTF printf
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#else
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#define DPRINTF(...)
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#endif
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#define MMIO_SIZE 0x1000
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#define CAPA_SIZE 0x10
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#define PORTSC 0x0044
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#define PORTSC_BEGIN PORTSC
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#define PORTSC_END (PORTSC + 4 * NB_PORTS)
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#define NB_PORTS 6 /* Number of downstream ports */
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typedef struct EHCIPacket EHCIPacket;
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typedef struct EHCIQueue EHCIQueue;
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typedef struct EHCIState EHCIState;
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/* EHCI spec version 1.0 Section 3.3
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*/
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typedef struct EHCIitd {
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uint32_t next;
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uint32_t transact[8];
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#define ITD_XACT_ACTIVE (1 << 31)
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#define ITD_XACT_DBERROR (1 << 30)
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#define ITD_XACT_BABBLE (1 << 29)
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#define ITD_XACT_XACTERR (1 << 28)
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#define ITD_XACT_LENGTH_MASK 0x0fff0000
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#define ITD_XACT_LENGTH_SH 16
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#define ITD_XACT_IOC (1 << 15)
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#define ITD_XACT_PGSEL_MASK 0x00007000
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#define ITD_XACT_PGSEL_SH 12
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#define ITD_XACT_OFFSET_MASK 0x00000fff
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uint32_t bufptr[7];
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#define ITD_BUFPTR_MASK 0xfffff000
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#define ITD_BUFPTR_SH 12
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#define ITD_BUFPTR_EP_MASK 0x00000f00
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#define ITD_BUFPTR_EP_SH 8
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#define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
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#define ITD_BUFPTR_DEVADDR_SH 0
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#define ITD_BUFPTR_DIRECTION (1 << 11)
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#define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
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#define ITD_BUFPTR_MAXPKT_SH 0
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#define ITD_BUFPTR_MULT_MASK 0x00000003
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#define ITD_BUFPTR_MULT_SH 0
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} EHCIitd;
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/* EHCI spec version 1.0 Section 3.4
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*/
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typedef struct EHCIsitd {
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uint32_t next; /* Standard next link pointer */
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uint32_t epchar;
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#define SITD_EPCHAR_IO (1 << 31)
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#define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
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#define SITD_EPCHAR_PORTNUM_SH 24
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#define SITD_EPCHAR_HUBADD_MASK 0x007f0000
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#define SITD_EPCHAR_HUBADDR_SH 16
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#define SITD_EPCHAR_EPNUM_MASK 0x00000f00
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#define SITD_EPCHAR_EPNUM_SH 8
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#define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
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uint32_t uframe;
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#define SITD_UFRAME_CMASK_MASK 0x0000ff00
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#define SITD_UFRAME_CMASK_SH 8
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#define SITD_UFRAME_SMASK_MASK 0x000000ff
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uint32_t results;
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#define SITD_RESULTS_IOC (1 << 31)
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#define SITD_RESULTS_PGSEL (1 << 30)
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#define SITD_RESULTS_TBYTES_MASK 0x03ff0000
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#define SITD_RESULTS_TYBYTES_SH 16
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#define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
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#define SITD_RESULTS_CPROGMASK_SH 8
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#define SITD_RESULTS_ACTIVE (1 << 7)
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#define SITD_RESULTS_ERR (1 << 6)
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#define SITD_RESULTS_DBERR (1 << 5)
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#define SITD_RESULTS_BABBLE (1 << 4)
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#define SITD_RESULTS_XACTERR (1 << 3)
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#define SITD_RESULTS_MISSEDUF (1 << 2)
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#define SITD_RESULTS_SPLITXSTATE (1 << 1)
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uint32_t bufptr[2];
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#define SITD_BUFPTR_MASK 0xfffff000
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#define SITD_BUFPTR_CURROFF_MASK 0x00000fff
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#define SITD_BUFPTR_TPOS_MASK 0x00000018
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#define SITD_BUFPTR_TPOS_SH 3
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#define SITD_BUFPTR_TCNT_MASK 0x00000007
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uint32_t backptr; /* Standard next link pointer */
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} EHCIsitd;
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/* EHCI spec version 1.0 Section 3.5
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*/
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typedef struct EHCIqtd {
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uint32_t next; /* Standard next link pointer */
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uint32_t altnext; /* Standard next link pointer */
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uint32_t token;
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#define QTD_TOKEN_DTOGGLE (1 << 31)
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#define QTD_TOKEN_TBYTES_MASK 0x7fff0000
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#define QTD_TOKEN_TBYTES_SH 16
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#define QTD_TOKEN_IOC (1 << 15)
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#define QTD_TOKEN_CPAGE_MASK 0x00007000
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#define QTD_TOKEN_CPAGE_SH 12
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#define QTD_TOKEN_CERR_MASK 0x00000c00
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#define QTD_TOKEN_CERR_SH 10
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#define QTD_TOKEN_PID_MASK 0x00000300
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#define QTD_TOKEN_PID_SH 8
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#define QTD_TOKEN_ACTIVE (1 << 7)
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#define QTD_TOKEN_HALT (1 << 6)
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#define QTD_TOKEN_DBERR (1 << 5)
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#define QTD_TOKEN_BABBLE (1 << 4)
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#define QTD_TOKEN_XACTERR (1 << 3)
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#define QTD_TOKEN_MISSEDUF (1 << 2)
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#define QTD_TOKEN_SPLITXSTATE (1 << 1)
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#define QTD_TOKEN_PING (1 << 0)
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uint32_t bufptr[5]; /* Standard buffer pointer */
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#define QTD_BUFPTR_MASK 0xfffff000
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#define QTD_BUFPTR_SH 12
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} EHCIqtd;
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/* EHCI spec version 1.0 Section 3.6
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*/
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typedef struct EHCIqh {
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uint32_t next; /* Standard next link pointer */
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/* endpoint characteristics */
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uint32_t epchar;
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#define QH_EPCHAR_RL_MASK 0xf0000000
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#define QH_EPCHAR_RL_SH 28
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#define QH_EPCHAR_C (1 << 27)
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#define QH_EPCHAR_MPLEN_MASK 0x07FF0000
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#define QH_EPCHAR_MPLEN_SH 16
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#define QH_EPCHAR_H (1 << 15)
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#define QH_EPCHAR_DTC (1 << 14)
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#define QH_EPCHAR_EPS_MASK 0x00003000
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#define QH_EPCHAR_EPS_SH 12
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#define EHCI_QH_EPS_FULL 0
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#define EHCI_QH_EPS_LOW 1
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#define EHCI_QH_EPS_HIGH 2
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#define EHCI_QH_EPS_RESERVED 3
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#define QH_EPCHAR_EP_MASK 0x00000f00
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#define QH_EPCHAR_EP_SH 8
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#define QH_EPCHAR_I (1 << 7)
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#define QH_EPCHAR_DEVADDR_MASK 0x0000007f
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#define QH_EPCHAR_DEVADDR_SH 0
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/* endpoint capabilities */
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uint32_t epcap;
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#define QH_EPCAP_MULT_MASK 0xc0000000
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#define QH_EPCAP_MULT_SH 30
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#define QH_EPCAP_PORTNUM_MASK 0x3f800000
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#define QH_EPCAP_PORTNUM_SH 23
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#define QH_EPCAP_HUBADDR_MASK 0x007f0000
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#define QH_EPCAP_HUBADDR_SH 16
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#define QH_EPCAP_CMASK_MASK 0x0000ff00
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#define QH_EPCAP_CMASK_SH 8
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#define QH_EPCAP_SMASK_MASK 0x000000ff
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#define QH_EPCAP_SMASK_SH 0
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uint32_t current_qtd; /* Standard next link pointer */
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uint32_t next_qtd; /* Standard next link pointer */
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uint32_t altnext_qtd;
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#define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
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#define QH_ALTNEXT_NAKCNT_SH 1
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uint32_t token; /* Same as QTD token */
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uint32_t bufptr[5]; /* Standard buffer pointer */
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#define BUFPTR_CPROGMASK_MASK 0x000000ff
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#define BUFPTR_FRAMETAG_MASK 0x0000001f
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#define BUFPTR_SBYTES_MASK 0x00000fe0
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#define BUFPTR_SBYTES_SH 5
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} EHCIqh;
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/* EHCI spec version 1.0 Section 3.7
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*/
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typedef struct EHCIfstn {
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uint32_t next; /* Standard next link pointer */
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uint32_t backptr; /* Standard next link pointer */
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} EHCIfstn;
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enum async_state {
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EHCI_ASYNC_NONE = 0,
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EHCI_ASYNC_INITIALIZED,
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EHCI_ASYNC_INFLIGHT,
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EHCI_ASYNC_FINISHED,
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};
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struct EHCIPacket {
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EHCIQueue *queue;
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QTAILQ_ENTRY(EHCIPacket) next;
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EHCIqtd qtd; /* copy of current QTD (being worked on) */
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uint32_t qtdaddr; /* address QTD read from */
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USBPacket packet;
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QEMUSGList sgl;
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int pid;
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enum async_state async;
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};
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struct EHCIQueue {
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EHCIState *ehci;
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QTAILQ_ENTRY(EHCIQueue) next;
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uint32_t seen;
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uint64_t ts;
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int async;
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int transact_ctr;
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/* cached data from guest - needs to be flushed
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* when guest removes an entry (doorbell, handshake sequence)
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*/
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EHCIqh qh; /* copy of current QH (being worked on) */
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uint32_t qhaddr; /* address QH read from */
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uint32_t qtdaddr; /* address QTD read from */
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int last_pid; /* pid of last packet executed */
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USBDevice *dev;
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QTAILQ_HEAD(pkts_head, EHCIPacket) packets;
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};
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typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
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struct EHCIState {
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USBBus bus;
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qemu_irq irq;
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MemoryRegion mem;
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DMAContext *dma;
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MemoryRegion mem_caps;
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MemoryRegion mem_opreg;
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MemoryRegion mem_ports;
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int companion_count;
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uint16_t capsbase;
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uint16_t opregbase;
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/* properties */
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uint32_t maxframes;
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/*
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* EHCI spec version 1.0 Section 2.3
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* Host Controller Operational Registers
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*/
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uint8_t caps[CAPA_SIZE];
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union {
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uint32_t opreg[PORTSC_BEGIN/sizeof(uint32_t)];
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struct {
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uint32_t usbcmd;
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uint32_t usbsts;
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uint32_t usbintr;
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uint32_t frindex;
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uint32_t ctrldssegment;
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uint32_t periodiclistbase;
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uint32_t asynclistaddr;
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uint32_t notused[9];
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uint32_t configflag;
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};
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};
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uint32_t portsc[NB_PORTS];
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/*
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* Internal states, shadow registers, etc
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*/
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QEMUTimer *frame_timer;
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QEMUBH *async_bh;
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uint32_t astate; /* Current state in asynchronous schedule */
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uint32_t pstate; /* Current state in periodic schedule */
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USBPort ports[NB_PORTS];
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USBPort *companion_ports[NB_PORTS];
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uint32_t usbsts_pending;
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uint32_t usbsts_frindex;
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EHCIQueueHead aqueues;
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EHCIQueueHead pqueues;
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/* which address to look at next */
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uint32_t a_fetch_addr;
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uint32_t p_fetch_addr;
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USBPacket ipacket;
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QEMUSGList isgl;
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uint64_t last_run_ns;
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uint32_t async_stepdown;
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uint32_t periodic_sched_active;
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bool int_req_by_async;
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};
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extern const VMStateDescription vmstate_ehci;
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void usb_ehci_initfn(EHCIState *s, DeviceState *dev);
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#define TYPE_PCI_EHCI "pci-ehci-usb"
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#define PCI_EHCI(obj) OBJECT_CHECK(EHCIPCIState, (obj), TYPE_PCI_EHCI)
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typedef struct EHCIPCIState {
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/*< private >*/
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PCIDevice pcidev;
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/*< public >*/
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EHCIState ehci;
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} EHCIPCIState;
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#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
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#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
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#define SYS_BUS_EHCI(obj) \
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OBJECT_CHECK(EHCISysBusState, (obj), TYPE_SYS_BUS_EHCI)
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#define SYS_BUS_EHCI_CLASS(class) \
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OBJECT_CLASS_CHECK(SysBusEHCIClass, (class), TYPE_SYS_BUS_EHCI)
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#define SYS_BUS_EHCI_GET_CLASS(obj) \
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OBJECT_GET_CLASS(SysBusEHCIClass, (obj), TYPE_SYS_BUS_EHCI)
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typedef struct EHCISysBusState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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EHCIState ehci;
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} EHCISysBusState;
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typedef struct SysBusEHCIClass {
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/*< private >*/
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SysBusDeviceClass parent_class;
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/*< public >*/
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uint16_t capsbase;
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uint16_t opregbase;
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} SysBusEHCIClass;
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#endif
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