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513598050a
Refactoring step on path to moving all CXL state out of MachineState. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Message-Id: <20220608145440.26106-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
256 lines
8.5 KiB
C
256 lines
8.5 KiB
C
/*
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* CXL ACPI Implementation
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*
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* Copyright(C) 2020 Intel Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/pci/pci_bridge.h"
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#include "hw/pci/pci_host.h"
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#include "hw/cxl/cxl.h"
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#include "hw/mem/memory-device.h"
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#include "hw/acpi/acpi.h"
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#include "hw/acpi/aml-build.h"
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#include "hw/acpi/bios-linker-loader.h"
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#include "hw/acpi/cxl.h"
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#include "qapi/error.h"
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#include "qemu/uuid.h"
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static void cedt_build_chbs(GArray *table_data, PXBDev *cxl)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(cxl->cxl.cxl_host_bridge);
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struct MemoryRegion *mr = sbd->mmio[0].memory;
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/* Type */
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build_append_int_noprefix(table_data, 0, 1);
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/* Reserved */
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build_append_int_noprefix(table_data, 0, 1);
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/* Record Length */
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build_append_int_noprefix(table_data, 32, 2);
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/* UID - currently equal to bus number */
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build_append_int_noprefix(table_data, cxl->bus_nr, 4);
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/* Version */
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build_append_int_noprefix(table_data, 1, 4);
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/* Reserved */
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build_append_int_noprefix(table_data, 0, 4);
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/* Base - subregion within a container that is in PA space */
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build_append_int_noprefix(table_data, mr->container->addr + mr->addr, 8);
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/* Length */
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build_append_int_noprefix(table_data, memory_region_size(mr), 8);
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}
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/*
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* CFMWS entries in CXL 2.0 ECN: CEDT CFMWS & QTG _DSM.
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* Interleave ways encoding in CXL 2.0 ECN: 3, 6, 12 and 16-way memory
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* interleaving.
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*/
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static void cedt_build_cfmws(GArray *table_data, CXLState *cxls)
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{
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GList *it;
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for (it = cxls->fixed_windows; it; it = it->next) {
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CXLFixedWindow *fw = it->data;
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int i;
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/* Type */
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build_append_int_noprefix(table_data, 1, 1);
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/* Reserved */
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build_append_int_noprefix(table_data, 0, 1);
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/* Record Length */
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build_append_int_noprefix(table_data, 36 + 4 * fw->num_targets, 2);
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/* Reserved */
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build_append_int_noprefix(table_data, 0, 4);
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/* Base HPA */
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build_append_int_noprefix(table_data, fw->mr.addr, 8);
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/* Window Size */
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build_append_int_noprefix(table_data, fw->size, 8);
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/* Host Bridge Interleave Ways */
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build_append_int_noprefix(table_data, fw->enc_int_ways, 1);
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/* Host Bridge Interleave Arithmetic */
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build_append_int_noprefix(table_data, 0, 1);
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/* Reserved */
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build_append_int_noprefix(table_data, 0, 2);
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/* Host Bridge Interleave Granularity */
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build_append_int_noprefix(table_data, fw->enc_int_gran, 4);
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/* Window Restrictions */
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build_append_int_noprefix(table_data, 0x0f, 2); /* No restrictions */
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/* QTG ID */
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build_append_int_noprefix(table_data, 0, 2);
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/* Host Bridge List (list of UIDs - currently bus_nr) */
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for (i = 0; i < fw->num_targets; i++) {
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g_assert(fw->target_hbs[i]);
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build_append_int_noprefix(table_data, fw->target_hbs[i]->bus_nr, 4);
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}
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}
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}
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static int cxl_foreach_pxb_hb(Object *obj, void *opaque)
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{
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Aml *cedt = opaque;
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if (object_dynamic_cast(obj, TYPE_PXB_CXL_DEVICE)) {
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cedt_build_chbs(cedt->buf, PXB_CXL_DEV(obj));
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}
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return 0;
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}
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void cxl_build_cedt(GArray *table_offsets, GArray *table_data,
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BIOSLinker *linker, const char *oem_id,
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const char *oem_table_id, CXLState *cxl_state)
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{
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Aml *cedt;
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AcpiTable table = { .sig = "CEDT", .rev = 1, .oem_id = oem_id,
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.oem_table_id = oem_table_id };
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acpi_add_table(table_offsets, table_data);
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acpi_table_begin(&table, table_data);
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cedt = init_aml_allocator();
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/* reserve space for CEDT header */
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object_child_foreach_recursive(object_get_root(), cxl_foreach_pxb_hb, cedt);
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cedt_build_cfmws(cedt->buf, cxl_state);
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/* copy AML table into ACPI tables blob and patch header there */
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g_array_append_vals(table_data, cedt->buf->data, cedt->buf->len);
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free_aml_allocator();
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acpi_table_end(linker, &table);
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}
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static Aml *__build_cxl_osc_method(void)
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{
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Aml *method, *if_uuid, *else_uuid, *if_arg1_not_1, *if_cxl, *if_caps_masked;
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Aml *a_ctrl = aml_local(0);
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Aml *a_cdw1 = aml_name("CDW1");
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method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
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/* CDW1 is used for the return value so is present whether or not a match occurs */
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aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
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/*
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* Generate shared section between:
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* CXL 2.0 - 9.14.2.1.4 and
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* PCI Firmware Specification 3.0
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* 4.5.1. _OSC Interface for PCI Host Bridge Devices
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* The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
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* identified by the Universal Unique IDentifier (UUID)
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* 33DB4D5B-1FF7-401C-9657-7441C03DD766
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* The _OSC interface for a CXL Host bridge is
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* identified by the UUID 68F2D50B-C469-4D8A-BD3D-941A103FD3FC
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* A CXL Host bridge is compatible with a PCI host bridge so
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* for the shared section match both.
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*/
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if_uuid = aml_if(
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aml_lor(aml_equal(aml_arg(0),
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aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")),
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aml_equal(aml_arg(0),
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aml_touuid("68F2D50B-C469-4D8A-BD3D-941A103FD3FC"))));
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aml_append(if_uuid, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
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aml_append(if_uuid, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
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aml_append(if_uuid, aml_store(aml_name("CDW3"), a_ctrl));
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/*
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*
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* Allows OS control for all 5 features:
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* PCIeHotplug SHPCHotplug PME AER PCIeCapability
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*/
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aml_append(if_uuid, aml_and(a_ctrl, aml_int(0x1F), a_ctrl));
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/*
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* Check _OSC revision.
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* PCI Firmware specification 3.3 and CXL 2.0 both use revision 1
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* Unknown Revision is CDW1 - BIT (3)
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*/
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if_arg1_not_1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
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aml_append(if_arg1_not_1, aml_or(a_cdw1, aml_int(0x08), a_cdw1));
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aml_append(if_uuid, if_arg1_not_1);
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if_caps_masked = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
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/* Capability bits were masked */
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aml_append(if_caps_masked, aml_or(a_cdw1, aml_int(0x10), a_cdw1));
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aml_append(if_uuid, if_caps_masked);
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aml_append(if_uuid, aml_store(aml_name("CDW2"), aml_name("SUPP")));
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aml_append(if_uuid, aml_store(aml_name("CDW3"), aml_name("CTRL")));
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/* Update DWORD3 (the return value) */
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aml_append(if_uuid, aml_store(a_ctrl, aml_name("CDW3")));
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/* CXL only section as per CXL 2.0 - 9.14.2.1.4 */
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if_cxl = aml_if(aml_equal(
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aml_arg(0), aml_touuid("68F2D50B-C469-4D8A-BD3D-941A103FD3FC")));
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/* CXL support field */
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aml_append(if_cxl, aml_create_dword_field(aml_arg(3), aml_int(12), "CDW4"));
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/* CXL capabilities */
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aml_append(if_cxl, aml_create_dword_field(aml_arg(3), aml_int(16), "CDW5"));
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aml_append(if_cxl, aml_store(aml_name("CDW4"), aml_name("SUPC")));
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aml_append(if_cxl, aml_store(aml_name("CDW5"), aml_name("CTRC")));
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/* CXL 2.0 Port/Device Register access */
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aml_append(if_cxl,
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aml_or(aml_name("CDW5"), aml_int(0x1), aml_name("CDW5")));
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aml_append(if_uuid, if_cxl);
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aml_append(if_uuid, aml_return(aml_arg(3)));
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aml_append(method, if_uuid);
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/*
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* If no UUID matched, return Unrecognized UUID via Arg3 DWord 1
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* ACPI 6.4 - 6.2.11
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* Unrecognised UUID - BIT(2)
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*/
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else_uuid = aml_else();
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aml_append(else_uuid,
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aml_or(aml_name("CDW1"), aml_int(0x4), aml_name("CDW1")));
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aml_append(else_uuid, aml_return(aml_arg(3)));
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aml_append(method, else_uuid);
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return method;
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}
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void build_cxl_osc_method(Aml *dev)
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{
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aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
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aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
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aml_append(dev, aml_name_decl("SUPC", aml_int(0)));
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aml_append(dev, aml_name_decl("CTRC", aml_int(0)));
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aml_append(dev, __build_cxl_osc_method());
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}
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