mirror of
https://gitlab.com/qemu-project/qemu
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65b4c8c759
Fix 'Identifer' -> 'Identifier' typo. Cc: Laurent Vivier <laurent@vivier.eu> Fixes:8c6df16ff6
("hw/char: add goldfish-tty") Fixes:8785559390
("hw/intc: add goldfish-pic") Fixes:2fde99ee31
("m68k: add an interrupt controller") Fixes:0791bc02b8
("m68k: add a system controller") Fixes:e1cecdca55
("m68k: add Virtual M68k Machine") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211103105311.3399293-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
150 lines
3.4 KiB
C
150 lines
3.4 KiB
C
/*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Virt system Controller
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*/
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#include "qemu/osdep.h"
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#include "hw/qdev-properties.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "sysemu/runstate.h"
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#include "hw/misc/virt_ctrl.h"
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enum {
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REG_FEATURES = 0x00,
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REG_CMD = 0x04,
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};
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#define FEAT_POWER_CTRL 0x00000001
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enum {
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CMD_NOOP,
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CMD_RESET,
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CMD_HALT,
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CMD_PANIC,
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};
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static uint64_t virt_ctrl_read(void *opaque, hwaddr addr, unsigned size)
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{
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VirtCtrlState *s = opaque;
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uint64_t value = 0;
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switch (addr) {
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case REG_FEATURES:
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value = FEAT_POWER_CTRL;
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: unimplemented register read 0x%02"HWADDR_PRIx"\n",
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__func__, addr);
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break;
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}
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trace_virt_ctrl_write(s, addr, size, value);
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return value;
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}
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static void virt_ctrl_write(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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{
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VirtCtrlState *s = opaque;
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trace_virt_ctrl_write(s, addr, size, value);
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switch (addr) {
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case REG_CMD:
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switch (value) {
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case CMD_NOOP:
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break;
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case CMD_RESET:
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qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
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break;
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case CMD_HALT:
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
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break;
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case CMD_PANIC:
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qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_PANIC);
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break;
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}
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s: unimplemented register write 0x%02"HWADDR_PRIx"\n",
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__func__, addr);
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break;
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}
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}
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static const MemoryRegionOps virt_ctrl_ops = {
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.read = virt_ctrl_read,
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.write = virt_ctrl_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.max_access_size = 4,
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.impl.max_access_size = 4,
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};
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static void virt_ctrl_reset(DeviceState *dev)
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{
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VirtCtrlState *s = VIRT_CTRL(dev);
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trace_virt_ctrl_reset(s);
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}
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static void virt_ctrl_realize(DeviceState *dev, Error **errp)
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{
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VirtCtrlState *s = VIRT_CTRL(dev);
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trace_virt_ctrl_instance_init(s);
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memory_region_init_io(&s->iomem, OBJECT(s), &virt_ctrl_ops, s,
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"virt-ctrl", 0x100);
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}
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static const VMStateDescription vmstate_virt_ctrl = {
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.name = "virt-ctrl",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(irq_enabled, VirtCtrlState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void virt_ctrl_instance_init(Object *obj)
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{
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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VirtCtrlState *s = VIRT_CTRL(obj);
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trace_virt_ctrl_instance_init(s);
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sysbus_init_mmio(dev, &s->iomem);
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sysbus_init_irq(dev, &s->irq);
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}
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static void virt_ctrl_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->reset = virt_ctrl_reset;
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dc->realize = virt_ctrl_realize;
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dc->vmsd = &vmstate_virt_ctrl;
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}
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static const TypeInfo virt_ctrl_info = {
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.name = TYPE_VIRT_CTRL,
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.parent = TYPE_SYS_BUS_DEVICE,
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.class_init = virt_ctrl_class_init,
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.instance_init = virt_ctrl_instance_init,
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.instance_size = sizeof(VirtCtrlState),
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};
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static void virt_ctrl_register_types(void)
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{
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type_register_static(&virt_ctrl_info);
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}
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type_init(virt_ctrl_register_types)
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