qemu/target-lm32
Blue Swirl a8a826a3c3 exec: refactor cpu_restore_state
Refactor common code around calls to cpu_restore_state().

tb_find_pc() has now no external users, make it static.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-16 08:35:24 +00:00
..
cpu-qom.h target-lm32: QOM'ify CPU 2012-04-12 01:07:41 +02:00
cpu.c target-lm32: Let cpu_lm32_init() return LM32CPU 2012-06-04 23:00:41 +02:00
cpu.h cpus: Pass CPUState to [qemu_]cpu_has_work() 2012-10-31 04:11:37 +01:00
helper.c Rename target_phys_addr_t to hwaddr 2012-10-23 08:58:25 -05:00
helper.h target-lm32: switch to AREG0 free mode 2012-09-15 17:44:32 +00:00
machine.c target-lm32: Don't overuse CPUState 2012-03-14 22:20:25 +01:00
Makefile.objs target-lm32: switch to AREG0 free mode 2012-09-15 17:44:32 +00:00
op_helper.c exec: refactor cpu_restore_state 2012-12-16 08:35:24 +00:00
README lm32: todo and documentation 2011-03-07 13:42:37 +01:00
TODO lm32: todo and documentation 2011-03-07 13:42:37 +01:00
translate.c TCG: Use gen_opc_instr_start from context instead of global variable. 2012-12-08 14:24:43 +00:00

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Programmatically terminate the emulator
----------------------------------------
Originally neither the LatticeMico32 nor its peripherals support a
mechanism to shut down the machine. Emulation aware programs can write to a
to a special register within the system control block to shut down the
virtual machine.  For more details see hw/lm32_sys.c. The lm32-evr is the
first BSP which instantiate this model. A (32 bit) write to 0xfff0000
causes a vm shutdown.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);