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a2735cf483
ISA 3.0B added a set of Floating-Point Status and Control Register (FPSCR) instructions: mffsce, mffscdrn, mffscdrni, mffscrn, mffscrni, mffsl. This patch adds support for 'mffscrn' and 'mffscrni' instructions. 'mffscrn' and 'mffscrni' are similar to 'mffsl', except they do not return the status bits (FI, FR, FPRF) and they also set the rounding mode in the FPSCR. On CPUs without support for 'mffscrn'/'mffscrni' (below ISA 3.0), the instructions will execute identically to 'mffs'. Signed-off-by: Paul A. Clarke <pc@us.ibm.com> Message-Id: <1568817081-1345-1-git-send-email-pc@us.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> |
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| .. | ||
| dfp-impl.inc.c | ||
| dfp-ops.inc.c | ||
| fp-impl.inc.c | ||
| fp-ops.inc.c | ||
| spe-impl.inc.c | ||
| spe-ops.inc.c | ||
| vmx-impl.inc.c | ||
| vmx-ops.inc.c | ||
| vsx-impl.inc.c | ||
| vsx-ops.inc.c | ||