Ben Widawsky 9dccb1216b hw/pci/cxl: Create a CXL bus type ... The easiest way to differentiate a CXL bus, and a PCIE bus is using a flag. A CXL bus, in hardware, is backward compatible with PCIE, and therefore the code tries pretty hard to keep them in sync as much as possible. The other way to implement this would be to try to cast the bus to the correct type. This is less code and useful for debugging via simply looking at the flags. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-13-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2022-05-13 06:13:36 -04:00
..
dec.c	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
dec.h	Include qemu-common.h exactly where needed	2019-06-12 13:20:20 +02:00
gen_pcie_root_port.c	hw/pcie-root-port: Fix hotplug for PCI devices requiring IO	2021-08-03 16:31:07 -04:00
i82801b11.c	nomaintainer: Fix Lesser GPL version number	2020-11-15 17:04:40 +01:00
ioh3420.c	Include migration/vmstate.h less	2019-08-16 13:31:52 +02:00
Kconfig	Kconfig: Compile PXB for ARM_VIRT	2021-01-17 06:42:54 -05:00
meson.build	meson: convert hw/pci-bridge	2020-08-21 06:30:28 -04:00
pci_bridge_dev.c	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
pci_expander_bridge.c	hw/pci/cxl: Create a CXL bus type	2022-05-13 06:13:36 -04:00
pcie_pci_bridge.c	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	2020-09-18 14:12:32 -04:00
pcie_root_port.c	pcie_root_port: Add hotplug disabling option	2020-03-08 09:18:29 -04:00
simba.c	Include qemu/module.h where needed, drop it from qemu-common.h	2019-06-12 13:18:33 +02:00
xio3130_downstream.c	pci: expose TYPE_XIO3130_DOWNSTREAM name	2022-03-06 05:08:23 -05:00
xio3130_upstream.c	pci-bridge/xio3130_upstream: Fix error handling	2022-03-06 05:08:23 -05:00