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592f0a9429
The system controller on PolarFire SoC is access via a mailbox. The control registers for this mailbox lie in the "IOSCB" region & the interrupt is cleared via write to the "SYSREG" region. It also has a QSPI controller, usually connected to a flash chip, that is used for storing FPGA bitstreams and used for In-Application Programming (IAP). Linux has an implementation of the system controller, through which the hwrng is accessed, leading to load/store access faults. Add the QSPI as unimplemented and a very basic (effectively unimplemented) version of the system controller's mailbox. Rather than purely marking the regions as unimplemented, service the mailbox requests by reporting failures and raising the interrupt so a guest can better handle the lack of support. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221117225518.4102575-4-conor@kernel.org> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
315 lines
11 KiB
C
315 lines
11 KiB
C
/*
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* Microchip PolarFire SoC IOSCB module emulation
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "hw/misc/mchp_pfsoc_ioscb.h"
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/*
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* The whole IOSCB module registers map into the system address at 0x3000_0000,
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* named as "System Port 0 (AXI-D0)".
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*/
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#define IOSCB_WHOLE_REG_SIZE 0x10000000
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#define IOSCB_SUBMOD_REG_SIZE 0x1000
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#define IOSCB_CCC_REG_SIZE 0x2000000
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#define IOSCB_CTRL_REG_SIZE 0x800
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#define IOSCB_QSPIXIP_REG_SIZE 0x200
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/*
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* There are many sub-modules in the IOSCB module.
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* See Microchip PolarFire SoC documentation (Register_Map.zip),
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* Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.htm
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*
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* The following are sub-modules offsets that are of concern.
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*/
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#define IOSCB_LANE01_BASE 0x06500000
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#define IOSCB_LANE23_BASE 0x06510000
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#define IOSCB_CTRL_BASE 0x07020000
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#define IOSCB_QSPIXIP_BASE 0x07020100
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#define IOSCB_MAILBOX_BASE 0x07020800
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#define IOSCB_CFG_BASE 0x07080000
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#define IOSCB_CCC_BASE 0x08000000
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#define IOSCB_PLL_MSS_BASE 0x0E001000
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#define IOSCB_CFM_MSS_BASE 0x0E002000
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#define IOSCB_PLL_DDR_BASE 0x0E010000
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#define IOSCB_BC_DDR_BASE 0x0E020000
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#define IOSCB_IO_CALIB_DDR_BASE 0x0E040000
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#define IOSCB_PLL_SGMII_BASE 0x0E080000
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#define IOSCB_DLL_SGMII_BASE 0x0E100000
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#define IOSCB_CFM_SGMII_BASE 0x0E200000
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#define IOSCB_BC_SGMII_BASE 0x0E400000
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#define IOSCB_IO_CALIB_SGMII_BASE 0x0E800000
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static uint64_t mchp_pfsoc_dummy_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
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"(size %d, offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, offset);
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return 0;
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}
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static void mchp_pfsoc_dummy_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
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"(size %d, value 0x%" PRIx64
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", offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, value, offset);
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}
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static const MemoryRegionOps mchp_pfsoc_dummy_ops = {
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.read = mchp_pfsoc_dummy_read,
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.write = mchp_pfsoc_dummy_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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/* All PLL modules in IOSCB have the same register layout */
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#define PLL_CTRL 0x04
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static uint64_t mchp_pfsoc_pll_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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uint32_t val = 0;
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switch (offset) {
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case PLL_CTRL:
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/* PLL is locked */
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val = BIT(25);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
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"(size %d, offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, offset);
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break;
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}
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return val;
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}
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static const MemoryRegionOps mchp_pfsoc_pll_ops = {
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.read = mchp_pfsoc_pll_read,
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.write = mchp_pfsoc_dummy_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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/* IO_CALIB_DDR submodule */
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#define IO_CALIB_DDR_IOC_REG1 0x08
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static uint64_t mchp_pfsoc_io_calib_ddr_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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uint32_t val = 0;
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switch (offset) {
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case IO_CALIB_DDR_IOC_REG1:
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/* calibration completed */
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val = BIT(2);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
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"(size %d, offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, offset);
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break;
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}
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return val;
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}
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static const MemoryRegionOps mchp_pfsoc_io_calib_ddr_ops = {
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.read = mchp_pfsoc_io_calib_ddr_read,
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.write = mchp_pfsoc_dummy_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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#define SERVICES_CR 0x50
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#define SERVICES_SR 0x54
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#define SERVICES_STATUS_SHIFT 16
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static uint64_t mchp_pfsoc_ctrl_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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uint32_t val = 0;
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switch (offset) {
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case SERVICES_SR:
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/*
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* Although some services have no error codes, most do. All services
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* that do implement errors, begin their error codes at 1. Treat all
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* service requests as failures & return 1.
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* See the "PolarFire® FPGA and PolarFire SoC FPGA System Services"
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* user guide for more information on service error codes.
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*/
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val = 1u << SERVICES_STATUS_SHIFT;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device read "
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"(size %d, offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, offset);
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}
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return val;
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}
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static void mchp_pfsoc_ctrl_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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MchpPfSoCIoscbState *s = opaque;
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switch (offset) {
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case SERVICES_CR:
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qemu_irq_raise(s->irq);
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "%s: unimplemented device write "
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"(size %d, value 0x%" PRIx64
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", offset 0x%" HWADDR_PRIx ")\n",
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__func__, size, value, offset);
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}
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}
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static const MemoryRegionOps mchp_pfsoc_ctrl_ops = {
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.read = mchp_pfsoc_ctrl_read,
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.write = mchp_pfsoc_ctrl_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void mchp_pfsoc_ioscb_realize(DeviceState *dev, Error **errp)
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{
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MchpPfSoCIoscbState *s = MCHP_PFSOC_IOSCB(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init(&s->container, OBJECT(s),
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"mchp.pfsoc.ioscb", IOSCB_WHOLE_REG_SIZE);
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sysbus_init_mmio(sbd, &s->container);
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/* add subregions for all sub-modules in IOSCB */
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memory_region_init_io(&s->lane01, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.lane01", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_LANE01_BASE, &s->lane01);
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memory_region_init_io(&s->lane23, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.lane23", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_LANE23_BASE, &s->lane23);
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memory_region_init_io(&s->ctrl, OBJECT(s), &mchp_pfsoc_ctrl_ops, s,
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"mchp.pfsoc.ioscb.ctrl", IOSCB_CTRL_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_CTRL_BASE, &s->ctrl);
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memory_region_init_io(&s->qspixip, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.qspixip", IOSCB_QSPIXIP_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_QSPIXIP_BASE, &s->qspixip);
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memory_region_init_io(&s->mailbox, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.mailbox", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_MAILBOX_BASE, &s->mailbox);
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memory_region_init_io(&s->cfg, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.cfg", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_CFG_BASE, &s->cfg);
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memory_region_init_io(&s->ccc, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.ccc", IOSCB_CCC_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_CCC_BASE, &s->ccc);
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memory_region_init_io(&s->pll_mss, OBJECT(s), &mchp_pfsoc_pll_ops, s,
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"mchp.pfsoc.ioscb.pll_mss", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_PLL_MSS_BASE, &s->pll_mss);
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memory_region_init_io(&s->cfm_mss, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.cfm_mss", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_CFM_MSS_BASE, &s->cfm_mss);
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memory_region_init_io(&s->pll_ddr, OBJECT(s), &mchp_pfsoc_pll_ops, s,
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"mchp.pfsoc.ioscb.pll_ddr", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_PLL_DDR_BASE, &s->pll_ddr);
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memory_region_init_io(&s->bc_ddr, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.bc_ddr", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_BC_DDR_BASE, &s->bc_ddr);
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memory_region_init_io(&s->io_calib_ddr, OBJECT(s),
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&mchp_pfsoc_io_calib_ddr_ops, s,
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"mchp.pfsoc.ioscb.io_calib_ddr",
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IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_DDR_BASE,
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&s->io_calib_ddr);
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memory_region_init_io(&s->pll_sgmii, OBJECT(s), &mchp_pfsoc_pll_ops, s,
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"mchp.pfsoc.ioscb.pll_sgmii", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_PLL_SGMII_BASE,
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&s->pll_sgmii);
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memory_region_init_io(&s->dll_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.dll_sgmii", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_DLL_SGMII_BASE,
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&s->dll_sgmii);
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memory_region_init_io(&s->cfm_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.cfm_sgmii", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_CFM_SGMII_BASE,
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&s->cfm_sgmii);
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memory_region_init_io(&s->bc_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops, s,
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"mchp.pfsoc.ioscb.bc_sgmii", IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_BC_SGMII_BASE,
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&s->bc_sgmii);
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memory_region_init_io(&s->io_calib_sgmii, OBJECT(s), &mchp_pfsoc_dummy_ops,
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s, "mchp.pfsoc.ioscb.io_calib_sgmii",
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IOSCB_SUBMOD_REG_SIZE);
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memory_region_add_subregion(&s->container, IOSCB_IO_CALIB_SGMII_BASE,
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&s->io_calib_sgmii);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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}
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static void mchp_pfsoc_ioscb_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "Microchip PolarFire SoC IOSCB modules";
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dc->realize = mchp_pfsoc_ioscb_realize;
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}
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static const TypeInfo mchp_pfsoc_ioscb_info = {
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.name = TYPE_MCHP_PFSOC_IOSCB,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MchpPfSoCIoscbState),
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.class_init = mchp_pfsoc_ioscb_class_init,
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};
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static void mchp_pfsoc_ioscb_register_types(void)
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{
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type_register_static(&mchp_pfsoc_ioscb_info);
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}
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type_init(mchp_pfsoc_ioscb_register_types)
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