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2f9db77ea8
Currently we implement the RAS register block within the NVIC device. It isn't really very tightly coupled with the NVIC proper, so instead move it out into a sysbus device of its own and have the top level ARMv7M container create it and map it into memory at the right address. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alexandre Iooss <erdnaxe@crans.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Luc Michel <luc@lmichel.fr> Reviewed-by: Damien Hedde <damien.hedde@greensocs.com> Message-id: 20210812093356.1946-2-peter.maydell@linaro.org
93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
/*
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* Arm M-profile RAS (Reliability, Availability and Serviceability) block
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*
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* Copyright (c) 2021 Linaro Limited
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "hw/misc/armv7m_ras.h"
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#include "qemu/log.h"
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static MemTxResult ras_read(void *opaque, hwaddr addr,
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uint64_t *data, unsigned size,
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MemTxAttrs attrs)
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{
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if (attrs.user) {
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return MEMTX_ERROR;
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}
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switch (addr) {
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case 0xe10: /* ERRIIDR */
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/* architect field = Arm; product/variant/revision 0 */
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*data = 0x43b;
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break;
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case 0xfc8: /* ERRDEVID */
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/* Minimal RAS: we implement 0 error record indexes */
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*data = 0;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
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(uint32_t)addr);
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*data = 0;
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break;
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}
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return MEMTX_OK;
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}
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static MemTxResult ras_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size,
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MemTxAttrs attrs)
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{
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if (attrs.user) {
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return MEMTX_ERROR;
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}
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switch (addr) {
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default:
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qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
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(uint32_t)addr);
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break;
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}
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return MEMTX_OK;
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}
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static const MemoryRegionOps ras_ops = {
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.read_with_attrs = ras_read,
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.write_with_attrs = ras_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void armv7m_ras_init(Object *obj)
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{
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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ARMv7MRAS *s = ARMV7M_RAS(obj);
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memory_region_init_io(&s->iomem, obj, &ras_ops,
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s, "armv7m-ras", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void armv7m_ras_class_init(ObjectClass *klass, void *data)
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{
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/* This device has no state: no need for vmstate or reset */
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}
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static const TypeInfo armv7m_ras_info = {
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.name = TYPE_ARMV7M_RAS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(ARMv7MRAS),
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.instance_init = armv7m_ras_init,
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.class_init = armv7m_ras_class_init,
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};
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static void armv7m_ras_register_types(void)
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{
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type_register_static(&armv7m_ras_info);
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}
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type_init(armv7m_ras_register_types);
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