qemu/target-lm32
Richard Henderson 4e5e121515 tcg: Remove gen_intermediate_code_pc
It is no longer used, so tidy up everything reached by it.
This includes the gen_opc_* arrays, the search_pc parameter
and the inline gen_intermediate_code_internal functions.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2015-10-07 20:36:52 +11:00
..
cpu-qom.h target-lm32: Use cpu_exec_interrupt qom hook 2014-09-25 18:54:22 +01:00
cpu.c cpu: Change cpu_exec_init() arg to cpu, not env 2015-07-09 15:20:40 +02:00
cpu.h target-*: Drop cpu_gen_code define 2015-10-07 20:36:50 +11:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
helper.c maint: remove / fix many doubled words 2015-09-11 10:21:38 +03:00
helper.h tcg: Invert the inclusion of helper.h 2014-05-28 09:33:54 -07:00
lm32-semi.c tcg: Invert the inclusion of helper.h 2014-05-28 09:33:54 -07:00
machine.c savevm: Remove all the unneeded version_minimum_id_old (rest) 2014-05-14 15:24:51 +02:00
Makefile.objs target-lm32: add semihosting support 2014-05-24 19:42:29 +02:00
op_helper.c vl: allow other threads to do qemu_system_vmstop_request 2014-06-23 16:36:13 +08:00
README lm32: remove lm32_sys 2014-05-24 19:43:52 +02:00
TODO target-lm32: add breakpoint/watchpoint support 2014-02-04 19:47:06 +01:00
translate.c tcg: Remove gen_intermediate_code_pc 2015-10-07 20:36:52 +11:00

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Semihosting
-----------
Semihosting on this target is supported. Some system calls like read, write
and exit are executed on the host if semihosting is enabled. See
target/lm32-semi.c for all supported system calls. Emulation aware programs
can use this mechanism to shut down the virtual machine and print to the
host console. See the tcg tests for an example.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);