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https://gitlab.com/qemu-project/qemu
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90166b71c4
The core file has register's value. But it does not include all registers value. Store the cpu status into QEMU note, and the user can get more information from vmcore. If you change QEMUCPUState, please count up QEMUCPUSTATE_VERSION. Signed-off-by: Wen Congyang <wency@cn.fujitsu.com> Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
383 lines
10 KiB
C
383 lines
10 KiB
C
/*
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* i386 memory mapping
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*
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* Copyright Fujitsu, Corp. 2011, 2012
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*
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* Authors:
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* Wen Congyang <wency@cn.fujitsu.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*
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*/
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#include "cpu.h"
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#include "cpu-all.h"
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#include "elf.h"
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#ifdef TARGET_X86_64
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typedef struct {
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target_ulong r15, r14, r13, r12, rbp, rbx, r11, r10;
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target_ulong r9, r8, rax, rcx, rdx, rsi, rdi, orig_rax;
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target_ulong rip, cs, eflags;
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target_ulong rsp, ss;
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target_ulong fs_base, gs_base;
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target_ulong ds, es, fs, gs;
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} x86_64_user_regs_struct;
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typedef struct {
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char pad1[32];
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uint32_t pid;
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char pad2[76];
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x86_64_user_regs_struct regs;
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char pad3[8];
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} x86_64_elf_prstatus;
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static int x86_64_write_elf64_note(write_core_dump_function f,
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CPUArchState *env, int id,
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void *opaque)
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{
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x86_64_user_regs_struct regs;
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Elf64_Nhdr *note;
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char *buf;
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int descsz, note_size, name_size = 5;
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const char *name = "CORE";
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int ret;
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regs.r15 = env->regs[15];
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regs.r14 = env->regs[14];
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regs.r13 = env->regs[13];
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regs.r12 = env->regs[12];
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regs.r11 = env->regs[11];
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regs.r10 = env->regs[10];
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regs.r9 = env->regs[9];
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regs.r8 = env->regs[8];
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regs.rbp = env->regs[R_EBP];
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regs.rsp = env->regs[R_ESP];
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regs.rdi = env->regs[R_EDI];
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regs.rsi = env->regs[R_ESI];
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regs.rdx = env->regs[R_EDX];
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regs.rcx = env->regs[R_ECX];
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regs.rbx = env->regs[R_EBX];
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regs.rax = env->regs[R_EAX];
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regs.rip = env->eip;
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regs.eflags = env->eflags;
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regs.orig_rax = 0; /* FIXME */
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regs.cs = env->segs[R_CS].selector;
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regs.ss = env->segs[R_SS].selector;
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regs.fs_base = env->segs[R_FS].base;
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regs.gs_base = env->segs[R_GS].base;
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regs.ds = env->segs[R_DS].selector;
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regs.es = env->segs[R_ES].selector;
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regs.fs = env->segs[R_FS].selector;
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regs.gs = env->segs[R_GS].selector;
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descsz = sizeof(x86_64_elf_prstatus);
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note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
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(descsz + 3) / 4) * 4;
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note = g_malloc(note_size);
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memset(note, 0, note_size);
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note->n_namesz = cpu_to_le32(name_size);
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note->n_descsz = cpu_to_le32(descsz);
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note->n_type = cpu_to_le32(NT_PRSTATUS);
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buf = (char *)note;
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buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
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memcpy(buf, name, name_size);
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buf += ((name_size + 3) / 4) * 4;
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memcpy(buf + 32, &id, 4); /* pr_pid */
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buf += descsz - sizeof(x86_64_user_regs_struct)-sizeof(target_ulong);
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memcpy(buf, ®s, sizeof(x86_64_user_regs_struct));
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ret = f(note, note_size, opaque);
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g_free(note);
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if (ret < 0) {
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return -1;
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}
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return 0;
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}
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#endif
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typedef struct {
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uint32_t ebx, ecx, edx, esi, edi, ebp, eax;
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unsigned short ds, __ds, es, __es;
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unsigned short fs, __fs, gs, __gs;
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uint32_t orig_eax, eip;
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unsigned short cs, __cs;
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uint32_t eflags, esp;
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unsigned short ss, __ss;
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} x86_user_regs_struct;
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typedef struct {
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char pad1[24];
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uint32_t pid;
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char pad2[44];
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x86_user_regs_struct regs;
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char pad3[4];
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} x86_elf_prstatus;
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static void x86_fill_elf_prstatus(x86_elf_prstatus *prstatus, CPUArchState *env,
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int id)
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{
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memset(prstatus, 0, sizeof(x86_elf_prstatus));
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prstatus->regs.ebp = env->regs[R_EBP] & 0xffffffff;
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prstatus->regs.esp = env->regs[R_ESP] & 0xffffffff;
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prstatus->regs.edi = env->regs[R_EDI] & 0xffffffff;
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prstatus->regs.esi = env->regs[R_ESI] & 0xffffffff;
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prstatus->regs.edx = env->regs[R_EDX] & 0xffffffff;
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prstatus->regs.ecx = env->regs[R_ECX] & 0xffffffff;
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prstatus->regs.ebx = env->regs[R_EBX] & 0xffffffff;
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prstatus->regs.eax = env->regs[R_EAX] & 0xffffffff;
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prstatus->regs.eip = env->eip & 0xffffffff;
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prstatus->regs.eflags = env->eflags & 0xffffffff;
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prstatus->regs.cs = env->segs[R_CS].selector;
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prstatus->regs.ss = env->segs[R_SS].selector;
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prstatus->regs.ds = env->segs[R_DS].selector;
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prstatus->regs.es = env->segs[R_ES].selector;
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prstatus->regs.fs = env->segs[R_FS].selector;
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prstatus->regs.gs = env->segs[R_GS].selector;
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prstatus->pid = id;
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}
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static int x86_write_elf64_note(write_core_dump_function f, CPUArchState *env,
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int id, void *opaque)
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{
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x86_elf_prstatus prstatus;
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Elf64_Nhdr *note;
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char *buf;
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int descsz, note_size, name_size = 5;
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const char *name = "CORE";
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int ret;
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x86_fill_elf_prstatus(&prstatus, env, id);
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descsz = sizeof(x86_elf_prstatus);
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note_size = ((sizeof(Elf64_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
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(descsz + 3) / 4) * 4;
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note = g_malloc(note_size);
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memset(note, 0, note_size);
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note->n_namesz = cpu_to_le32(name_size);
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note->n_descsz = cpu_to_le32(descsz);
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note->n_type = cpu_to_le32(NT_PRSTATUS);
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buf = (char *)note;
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buf += ((sizeof(Elf64_Nhdr) + 3) / 4) * 4;
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memcpy(buf, name, name_size);
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buf += ((name_size + 3) / 4) * 4;
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memcpy(buf, &prstatus, sizeof(prstatus));
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ret = f(note, note_size, opaque);
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g_free(note);
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if (ret < 0) {
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return -1;
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}
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return 0;
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}
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int cpu_write_elf64_note(write_core_dump_function f, CPUArchState *env,
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int cpuid, void *opaque)
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{
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int ret;
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#ifdef TARGET_X86_64
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bool lma = !!(first_cpu->hflags & HF_LMA_MASK);
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if (lma) {
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ret = x86_64_write_elf64_note(f, env, cpuid, opaque);
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} else {
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#endif
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ret = x86_write_elf64_note(f, env, cpuid, opaque);
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#ifdef TARGET_X86_64
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}
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#endif
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return ret;
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}
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int cpu_write_elf32_note(write_core_dump_function f, CPUArchState *env,
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int cpuid, void *opaque)
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{
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x86_elf_prstatus prstatus;
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Elf32_Nhdr *note;
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char *buf;
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int descsz, note_size, name_size = 5;
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const char *name = "CORE";
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int ret;
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x86_fill_elf_prstatus(&prstatus, env, cpuid);
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descsz = sizeof(x86_elf_prstatus);
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note_size = ((sizeof(Elf32_Nhdr) + 3) / 4 + (name_size + 3) / 4 +
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(descsz + 3) / 4) * 4;
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note = g_malloc(note_size);
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memset(note, 0, note_size);
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note->n_namesz = cpu_to_le32(name_size);
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note->n_descsz = cpu_to_le32(descsz);
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note->n_type = cpu_to_le32(NT_PRSTATUS);
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buf = (char *)note;
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buf += ((sizeof(Elf32_Nhdr) + 3) / 4) * 4;
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memcpy(buf, name, name_size);
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buf += ((name_size + 3) / 4) * 4;
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memcpy(buf, &prstatus, sizeof(prstatus));
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ret = f(note, note_size, opaque);
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g_free(note);
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if (ret < 0) {
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return -1;
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}
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return 0;
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}
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/*
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* please count up QEMUCPUSTATE_VERSION if you have changed definition of
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* QEMUCPUState, and modify the tools using this information accordingly.
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*/
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#define QEMUCPUSTATE_VERSION (1)
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struct QEMUCPUSegment {
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uint32_t selector;
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uint32_t limit;
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uint32_t flags;
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uint32_t pad;
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uint64_t base;
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};
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typedef struct QEMUCPUSegment QEMUCPUSegment;
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struct QEMUCPUState {
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uint32_t version;
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uint32_t size;
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uint64_t rax, rbx, rcx, rdx, rsi, rdi, rsp, rbp;
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uint64_t r8, r9, r10, r11, r12, r13, r14, r15;
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uint64_t rip, rflags;
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QEMUCPUSegment cs, ds, es, fs, gs, ss;
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QEMUCPUSegment ldt, tr, gdt, idt;
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uint64_t cr[5];
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};
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typedef struct QEMUCPUState QEMUCPUState;
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static void copy_segment(QEMUCPUSegment *d, SegmentCache *s)
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{
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d->pad = 0;
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d->selector = s->selector;
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d->limit = s->limit;
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d->flags = s->flags;
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d->base = s->base;
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}
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static void qemu_get_cpustate(QEMUCPUState *s, CPUArchState *env)
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{
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memset(s, 0, sizeof(QEMUCPUState));
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s->version = QEMUCPUSTATE_VERSION;
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s->size = sizeof(QEMUCPUState);
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s->rax = env->regs[R_EAX];
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s->rbx = env->regs[R_EBX];
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s->rcx = env->regs[R_ECX];
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s->rdx = env->regs[R_EDX];
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s->rsi = env->regs[R_ESI];
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s->rdi = env->regs[R_EDI];
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s->rsp = env->regs[R_ESP];
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s->rbp = env->regs[R_EBP];
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#ifdef TARGET_X86_64
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s->r8 = env->regs[8];
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s->r9 = env->regs[9];
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s->r10 = env->regs[10];
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s->r11 = env->regs[11];
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s->r12 = env->regs[12];
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s->r13 = env->regs[13];
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s->r14 = env->regs[14];
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s->r15 = env->regs[15];
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#endif
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s->rip = env->eip;
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s->rflags = env->eflags;
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copy_segment(&s->cs, &env->segs[R_CS]);
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copy_segment(&s->ds, &env->segs[R_DS]);
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copy_segment(&s->es, &env->segs[R_ES]);
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copy_segment(&s->fs, &env->segs[R_FS]);
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copy_segment(&s->gs, &env->segs[R_GS]);
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copy_segment(&s->ss, &env->segs[R_SS]);
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copy_segment(&s->ldt, &env->ldt);
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copy_segment(&s->tr, &env->tr);
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copy_segment(&s->gdt, &env->gdt);
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copy_segment(&s->idt, &env->idt);
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s->cr[0] = env->cr[0];
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s->cr[1] = env->cr[1];
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s->cr[2] = env->cr[2];
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s->cr[3] = env->cr[3];
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s->cr[4] = env->cr[4];
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}
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static inline int cpu_write_qemu_note(write_core_dump_function f,
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CPUArchState *env,
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void *opaque,
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int type)
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{
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QEMUCPUState state;
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Elf64_Nhdr *note64;
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Elf32_Nhdr *note32;
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void *note;
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char *buf;
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int descsz, note_size, name_size = 5, note_head_size;
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const char *name = "QEMU";
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int ret;
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qemu_get_cpustate(&state, env);
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descsz = sizeof(state);
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if (type == 0) {
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note_head_size = sizeof(Elf32_Nhdr);
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} else {
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note_head_size = sizeof(Elf64_Nhdr);
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}
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note_size = ((note_head_size + 3) / 4 + (name_size + 3) / 4 +
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(descsz + 3) / 4) * 4;
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note = g_malloc(note_size);
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memset(note, 0, note_size);
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if (type == 0) {
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note32 = note;
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note32->n_namesz = cpu_to_le32(name_size);
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note32->n_descsz = cpu_to_le32(descsz);
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note32->n_type = 0;
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} else {
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note64 = note;
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note64->n_namesz = cpu_to_le32(name_size);
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note64->n_descsz = cpu_to_le32(descsz);
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note64->n_type = 0;
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}
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buf = note;
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buf += ((note_head_size + 3) / 4) * 4;
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memcpy(buf, name, name_size);
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buf += ((name_size + 3) / 4) * 4;
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memcpy(buf, &state, sizeof(state));
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ret = f(note, note_size, opaque);
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g_free(note);
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if (ret < 0) {
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return -1;
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}
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return 0;
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}
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int cpu_write_elf64_qemunote(write_core_dump_function f, CPUArchState *env,
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void *opaque)
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{
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return cpu_write_qemu_note(f, env, opaque, 1);
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}
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int cpu_write_elf32_qemunote(write_core_dump_function f, CPUArchState *env,
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void *opaque)
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{
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return cpu_write_qemu_note(f, env, opaque, 0);
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}
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