qemu/target
Michael Clark 8c59f5c1b5
RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10
Privileged ISA v1.9.1 defines mscounteren and mucounteren:

* mscounteren contains a mask of counters available to S-mode
* mucounteren contains a mask of counters available to U-mode

Privileged ISA v1.10 defines mcounteren and scounteren:

* mcounteren contains a mask of counters available to S-mode
* scounteren contains a mask of counters available to U-mode

mcounteren and scounteren CSR registers were implemented
however they were not honoured for counter accesses when
the privilege ISA was >= v1.10. This fix solves the issue
by coalescing the counter enable registers. In addition
the code now  generates illegal instruction exceptions
for accesses to the counter enabled registers depending
on the privileged ISA version.

- Coalesce mscounteren and mcounteren into one variable
- Coalesce mucounteren and scounteren into one variable
- Makes mcounteren and scounteren CSR accesses generate
  illegal instructions when the privileged ISA <= v1.9.1
- Makes mscounteren and mucounteren CSR accesses generate
  illegal instructions when the privileged ISA >= v1.10

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
2018-05-06 10:39:38 +12:00
..
alpha icount: fix cpu_restore_state_from_tb for non-tb-exit cases 2018-04-11 09:05:22 +10:00
arm target/arm: Make PMOVSCLR and PMUSERENR 64 bits wide 2018-04-26 11:04:39 +01:00
cris icount: fix cpu_restore_state_from_tb for non-tb-exit cases 2018-04-11 09:05:22 +10:00
hppa tcg: Improve TCGv_ptr support 2018-05-01 11:56:16 -07:00
i386 i386: Don't automatically enable FEAT_KVM_HINTS bits 2018-04-16 13:36:52 -03:00
lm32 cpu: get rid of unused cpu_init() defines 2018-03-19 14:10:36 -03:00
m68k m68k: remove dead code (Coverity CID1390617) 2018-05-01 15:37:20 +02:00
microblaze target-microblaze: mmu: Make the TLBX MISS bit read-only 2018-04-30 16:43:20 +02:00
mips cpu: get rid of unused cpu_init() defines 2018-03-19 14:10:36 -03:00
moxie icount: fix cpu_restore_state_from_tb for non-tb-exit cases 2018-04-11 09:05:22 +10:00
nios2 cpu: get rid of unused cpu_init() defines 2018-03-19 14:10:36 -03:00
openrisc icount: fix cpu_restore_state_from_tb for non-tb-exit cases 2018-04-11 09:05:22 +10:00
ppc QAPI patches for 2018-05-04 2018-05-04 13:49:08 +01:00
riscv RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10 2018-05-06 10:39:38 +12:00
s390x QAPI patches for 2018-05-04 2018-05-04 13:49:08 +01:00
sh4 cpu: get rid of unused cpu_init() defines 2018-03-19 14:10:36 -03:00
sparc cpu: get rid of unused cpu_init() defines 2018-03-19 14:10:36 -03:00
tilegx cpu: get rid of unused cpu_init() defines 2018-03-19 14:10:36 -03:00
tricore icount: fix cpu_restore_state_from_tb for non-tb-exit cases 2018-04-11 09:05:22 +10:00
unicore32 cpu: get rid of unused cpu_init() defines 2018-03-19 14:10:36 -03:00
xtensa icount: fix cpu_restore_state_from_tb for non-tb-exit cases 2018-04-11 09:05:22 +10:00