mirror of
https://gitlab.com/qemu-project/qemu
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bdff8123f2
Switch the microblaze target from the old unassigned_access hook to the transaction_failed hook. The notable difference is that rather than it being called for all physical memory accesses which fail (including those made by DMA devices or by the gdbstub), it is only called for those made by the CPU via its MMU. For microblaze this makes no difference because none of the target CPU code needs to make loads or stores by physical address. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> [EI: Add space in qemu_log()] Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
523 lines
14 KiB
C
523 lines
14 KiB
C
/*
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* Microblaze helper routines.
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*
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* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
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* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "qemu/host-utils.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "fpu/softfloat.h"
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#define D(x)
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#if !defined(CONFIG_USER_ONLY)
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/* Try to fill the TLB and return an exception if error. If retaddr is
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* NULL, it means that the function was called in C code (i.e. not
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* from generated code or from helper.c)
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*/
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void tlb_fill(CPUState *cs, target_ulong addr, int size,
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MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
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{
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int ret;
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ret = mb_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
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if (unlikely(ret)) {
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/* now we have a real cpu fault */
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cpu_loop_exit_restore(cs, retaddr);
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}
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}
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#endif
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void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
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{
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int test = ctrl & STREAM_TEST;
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int atomic = ctrl & STREAM_ATOMIC;
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int control = ctrl & STREAM_CONTROL;
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int nonblock = ctrl & STREAM_NONBLOCK;
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int exception = ctrl & STREAM_EXCEPTION;
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qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
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id, data,
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test ? "t" : "",
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nonblock ? "n" : "",
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exception ? "e" : "",
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control ? "c" : "",
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atomic ? "a" : "");
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}
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uint32_t helper_get(uint32_t id, uint32_t ctrl)
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{
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int test = ctrl & STREAM_TEST;
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int atomic = ctrl & STREAM_ATOMIC;
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int control = ctrl & STREAM_CONTROL;
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int nonblock = ctrl & STREAM_NONBLOCK;
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int exception = ctrl & STREAM_EXCEPTION;
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qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
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id,
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test ? "t" : "",
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nonblock ? "n" : "",
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exception ? "e" : "",
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control ? "c" : "",
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atomic ? "a" : "");
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return 0xdead0000 | id;
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}
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void helper_raise_exception(CPUMBState *env, uint32_t index)
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{
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CPUState *cs = CPU(mb_env_get_cpu(env));
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cs->exception_index = index;
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cpu_loop_exit(cs);
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}
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void helper_debug(CPUMBState *env)
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{
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int i;
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qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]);
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qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
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"debug[%x] imm=%x iflags=%x\n",
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env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
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env->debug, env->imm, env->iflags);
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qemu_log("btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) eip=%d ie=%d\n",
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env->btaken, env->btarget,
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(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
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(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
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(bool)(env->sregs[SR_MSR] & MSR_EIP),
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(bool)(env->sregs[SR_MSR] & MSR_IE));
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for (i = 0; i < 32; i++) {
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qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
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if ((i + 1) % 4 == 0)
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qemu_log("\n");
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}
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qemu_log("\n\n");
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}
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static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
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{
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uint32_t cout = 0;
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if ((b == ~0) && cin)
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cout = 1;
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else if ((~0 - a) < (b + cin))
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cout = 1;
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return cout;
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}
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uint32_t helper_cmp(uint32_t a, uint32_t b)
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{
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uint32_t t;
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t = b + ~a + 1;
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if ((b & 0x80000000) ^ (a & 0x80000000))
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t = (t & 0x7fffffff) | (b & 0x80000000);
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return t;
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}
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uint32_t helper_cmpu(uint32_t a, uint32_t b)
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{
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uint32_t t;
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t = b + ~a + 1;
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if ((b & 0x80000000) ^ (a & 0x80000000))
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t = (t & 0x7fffffff) | (a & 0x80000000);
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return t;
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}
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uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
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{
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return compute_carry(a, b, cf);
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}
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static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
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{
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if (b == 0) {
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env->sregs[SR_MSR] |= MSR_DZ;
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if ((env->sregs[SR_MSR] & MSR_EE)
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&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
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env->sregs[SR_ESR] = ESR_EC_DIVZERO;
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helper_raise_exception(env, EXCP_HW_EXCP);
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}
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return 0;
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}
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env->sregs[SR_MSR] &= ~MSR_DZ;
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return 1;
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}
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uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
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{
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if (!div_prepare(env, a, b)) {
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return 0;
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}
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return (int32_t)a / (int32_t)b;
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}
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uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
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{
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if (!div_prepare(env, a, b)) {
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return 0;
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}
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return a / b;
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}
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/* raise FPU exception. */
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static void raise_fpu_exception(CPUMBState *env)
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{
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env->sregs[SR_ESR] = ESR_EC_FPU;
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helper_raise_exception(env, EXCP_HW_EXCP);
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}
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static void update_fpu_flags(CPUMBState *env, int flags)
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{
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int raise = 0;
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if (flags & float_flag_invalid) {
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env->sregs[SR_FSR] |= FSR_IO;
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raise = 1;
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}
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if (flags & float_flag_divbyzero) {
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env->sregs[SR_FSR] |= FSR_DZ;
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raise = 1;
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}
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if (flags & float_flag_overflow) {
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env->sregs[SR_FSR] |= FSR_OF;
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raise = 1;
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}
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if (flags & float_flag_underflow) {
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env->sregs[SR_FSR] |= FSR_UF;
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raise = 1;
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}
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if (raise
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&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
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&& (env->sregs[SR_MSR] & MSR_EE)) {
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raise_fpu_exception(env);
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}
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}
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uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fd, fa, fb;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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fd.f = float32_add(fa.f, fb.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags);
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return fd.l;
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}
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uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fd, fa, fb;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags);
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return fd.l;
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}
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uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fd, fa, fb;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags);
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return fd.l;
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}
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uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fd, fa, fb;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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fd.f = float32_div(fb.f, fa.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags);
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return fd.l;
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}
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uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fa, fb;
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uint32_t r = 0;
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fa.l = a;
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fb.l = b;
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if (float32_is_signaling_nan(fa.f, &env->fp_status) ||
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float32_is_signaling_nan(fb.f, &env->fp_status)) {
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update_fpu_flags(env, float_flag_invalid);
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r = 1;
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}
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if (float32_is_quiet_nan(fa.f, &env->fp_status) ||
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float32_is_quiet_nan(fb.f, &env->fp_status)) {
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r = 1;
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}
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return r;
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}
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uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fa, fb;
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int r;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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r = float32_lt(fb.f, fa.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags & float_flag_invalid);
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return r;
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}
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uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fa, fb;
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int flags;
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int r;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fb.l = b;
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r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags & float_flag_invalid);
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return r;
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}
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uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fa, fb;
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int flags;
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int r;
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fa.l = a;
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fb.l = b;
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set_float_exception_flags(0, &env->fp_status);
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r = float32_le(fa.f, fb.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags & float_flag_invalid);
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return r;
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}
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uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fa, fb;
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int flags, r;
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fa.l = a;
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fb.l = b;
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set_float_exception_flags(0, &env->fp_status);
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r = float32_lt(fa.f, fb.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags & float_flag_invalid);
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return r;
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}
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uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fa, fb;
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int flags, r;
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fa.l = a;
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fb.l = b;
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set_float_exception_flags(0, &env->fp_status);
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r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags & float_flag_invalid);
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return r;
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}
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uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
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{
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CPU_FloatU fa, fb;
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int flags, r;
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fa.l = a;
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fb.l = b;
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set_float_exception_flags(0, &env->fp_status);
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r = !float32_lt(fa.f, fb.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags & float_flag_invalid);
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return r;
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}
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uint32_t helper_flt(CPUMBState *env, uint32_t a)
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{
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CPU_FloatU fd, fa;
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fa.l = a;
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fd.f = int32_to_float32(fa.l, &env->fp_status);
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return fd.l;
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}
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uint32_t helper_fint(CPUMBState *env, uint32_t a)
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{
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CPU_FloatU fa;
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uint32_t r;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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r = float32_to_int32(fa.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags);
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return r;
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}
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uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
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{
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CPU_FloatU fd, fa;
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int flags;
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set_float_exception_flags(0, &env->fp_status);
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fa.l = a;
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fd.l = float32_sqrt(fa.f, &env->fp_status);
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flags = get_float_exception_flags(&env->fp_status);
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update_fpu_flags(env, flags);
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return fd.l;
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}
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uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
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{
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unsigned int i;
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uint32_t mask = 0xff000000;
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for (i = 0; i < 4; i++) {
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if ((a & mask) == (b & mask))
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return i + 1;
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mask >>= 8;
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}
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return 0;
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}
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void helper_memalign(CPUMBState *env, target_ulong addr,
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uint32_t dr, uint32_t wr,
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uint32_t mask)
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{
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if (addr & mask) {
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qemu_log_mask(CPU_LOG_INT,
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"unaligned access addr=" TARGET_FMT_lx
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" mask=%x, wr=%d dr=r%d\n",
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addr, mask, wr, dr);
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env->sregs[SR_EAR] = addr;
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env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
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| (dr & 31) << 5;
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if (mask == 3) {
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env->sregs[SR_ESR] |= 1 << 11;
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}
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if (!(env->sregs[SR_MSR] & MSR_EE)) {
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return;
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}
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helper_raise_exception(env, EXCP_HW_EXCP);
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}
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}
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void helper_stackprot(CPUMBState *env, target_ulong addr)
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{
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if (addr < env->slr || addr > env->shr) {
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qemu_log_mask(CPU_LOG_INT, "Stack protector violation at "
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TARGET_FMT_lx " %x %x\n",
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addr, env->slr, env->shr);
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env->sregs[SR_EAR] = addr;
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env->sregs[SR_ESR] = ESR_EC_STACKPROT;
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helper_raise_exception(env, EXCP_HW_EXCP);
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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/* Writes/reads to the MMU's special regs end up here. */
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uint32_t helper_mmu_read(CPUMBState *env, uint32_t ext, uint32_t rn)
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{
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return mmu_read(env, ext, rn);
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}
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void helper_mmu_write(CPUMBState *env, uint32_t ext, uint32_t rn, uint32_t v)
|
|
{
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|
mmu_write(env, ext, rn, v);
|
|
}
|
|
|
|
void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
|
|
unsigned size, MMUAccessType access_type,
|
|
int mmu_idx, MemTxAttrs attrs,
|
|
MemTxResult response, uintptr_t retaddr)
|
|
{
|
|
MicroBlazeCPU *cpu;
|
|
CPUMBState *env;
|
|
qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx
|
|
" physaddr 0x" TARGET_FMT_plx " size %d access type %s\n",
|
|
addr, physaddr, size,
|
|
access_type == MMU_INST_FETCH ? "INST_FETCH" :
|
|
(access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE"));
|
|
cpu = MICROBLAZE_CPU(cs);
|
|
env = &cpu->env;
|
|
|
|
cpu_restore_state(cs, retaddr, true);
|
|
if (!(env->sregs[SR_MSR] & MSR_EE)) {
|
|
return;
|
|
}
|
|
|
|
env->sregs[SR_EAR] = addr;
|
|
if (access_type == MMU_INST_FETCH) {
|
|
if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
|
|
env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
|
|
helper_raise_exception(env, EXCP_HW_EXCP);
|
|
}
|
|
} else {
|
|
if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
|
|
env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
|
|
helper_raise_exception(env, EXCP_HW_EXCP);
|
|
}
|
|
}
|
|
}
|
|
#endif
|