qemu/target-lm32
Richard Henderson 4910e6e42e target-*: dfilter support for in_asm
The arm target was handled by 06486077, but other targets
were ignored.  This handles all the rest which actually support
disassembly (that is, skipping moxie and tilegx).

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-06-05 09:26:24 -07:00
..
cpu-qom.h target-lm32: make cpu-qom.h not target specific 2016-05-19 13:08:04 +02:00
cpu.c cpu: move exec-all.h inclusion out of cpu.h 2016-05-19 16:42:29 +02:00
cpu.h cpu: move exec-all.h inclusion out of cpu.h 2016-05-19 16:42:29 +02:00
gdbstub.c qemu-common: push cpu.h inclusion out of qemu-common.h 2016-05-19 16:42:29 +02:00
helper.c cpu: move exec-all.h inclusion out of cpu.h 2016-05-19 16:42:29 +02:00
helper.h tcg: Invert the inclusion of helper.h 2014-05-28 09:33:54 -07:00
lm32-semi.c lm32: Clean up includes 2016-01-29 15:07:22 +00:00
machine.c qemu-common: push cpu.h inclusion out of qemu-common.h 2016-05-19 16:42:29 +02:00
Makefile.objs target-lm32: add semihosting support 2014-05-24 19:42:29 +02:00
op_helper.c cpu: move exec-all.h inclusion out of cpu.h 2016-05-19 16:42:29 +02:00
README lm32: remove lm32_sys 2014-05-24 19:43:52 +02:00
TODO target-lm32: add breakpoint/watchpoint support 2014-02-04 19:47:06 +01:00
translate.c target-*: dfilter support for in_asm 2016-06-05 09:26:24 -07:00

LatticeMico32 target
--------------------

General
-------
All opcodes including the JUART CSRs are supported.


JTAG UART
---------
JTAG UART is routed to a serial console device. For the current boards it
is the second one. Ie to enable it in the qemu virtual console window use
the following command line parameters:
  -serial vc -serial vc
This will make serial0 (the lm32_uart) and serial1 (the JTAG UART)
available as virtual consoles.


Semihosting
-----------
Semihosting on this target is supported. Some system calls like read, write
and exit are executed on the host if semihosting is enabled. See
target/lm32-semi.c for all supported system calls. Emulation aware programs
can use this mechanism to shut down the virtual machine and print to the
host console. See the tcg tests for an example.


Special instructions
--------------------
The translation recognizes one special instruction to halt the cpu:
  and r0, r0, r0
On real hardware this instruction is a nop. It is not used by GCC and
should (hopefully) not be used within hand-crafted assembly.
Insert this instruction in your idle loop to reduce the cpu load on the
host.


Ignoring the MSB of the address bus
-----------------------------------
Some SoC ignores the MSB on the address bus. Thus creating a shadow memory
area. As a general rule, 0x00000000-0x7fffffff is cached, whereas
0x80000000-0xffffffff is not cached and used to access IO devices. This
behaviour can be enabled with:
  cpu_lm32_set_phys_msb_ignore(env, 1);