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8700ee15de
Previously not all references mentioned any spec version at all. Given r3.1 is the current specification available for evaluation at www.computeexpresslink.org update references to refer to that. Hopefully this won't become a never ending job. A few structure definitions have been updated to add new fields. Defaults of 0 and read only are valid choices for these new DVSEC registers so go with that for now. There are additional error codes and some of the 'questions' in the comments are resolved now. Update documentation reference to point to the CXL r3.1 specification with naming closer to what is on the cover. For cases where there are structure version numbers, add defines so they can be found next to the register definitions. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20240126121636.24611-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
446 lines
15 KiB
C
446 lines
15 KiB
C
/*
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* CXL Utility library for devices
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*
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* Copyright(C) 2020 Intel Corporation.
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See the
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* COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/cxl/cxl.h"
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/*
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* Device registers have no restrictions per the spec, and so fall back to the
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* default memory mapped register rules in CXL r3.1 Section 8.2:
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* Software shall use CXL.io Memory Read and Write to access memory mapped
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* register defined in this section. Unless otherwise specified, software
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* shall restrict the accesses width based on the following:
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* • A 32 bit register shall be accessed as a 1 Byte, 2 Bytes or 4 Bytes
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* quantity.
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* • A 64 bit register shall be accessed as a 1 Byte, 2 Bytes, 4 Bytes or 8
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* Bytes
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* • The address shall be a multiple of the access width, e.g. when
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* accessing a register as a 4 Byte quantity, the address shall be
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* multiple of 4.
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* • The accesses shall map to contiguous bytes.If these rules are not
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* followed, the behavior is undefined
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*/
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static uint64_t caps_reg_read(void *opaque, hwaddr offset, unsigned size)
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{
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CXLDeviceState *cxl_dstate = opaque;
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switch (size) {
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case 4:
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return cxl_dstate->caps_reg_state32[offset / size];
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case 8:
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return cxl_dstate->caps_reg_state64[offset / size];
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default:
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g_assert_not_reached();
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}
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}
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static uint64_t dev_reg_read(void *opaque, hwaddr offset, unsigned size)
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{
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CXLDeviceState *cxl_dstate = opaque;
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switch (size) {
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case 1:
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return cxl_dstate->dev_reg_state[offset];
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case 2:
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return cxl_dstate->dev_reg_state16[offset / size];
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case 4:
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return cxl_dstate->dev_reg_state32[offset / size];
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case 8:
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return cxl_dstate->dev_reg_state64[offset / size];
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default:
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g_assert_not_reached();
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}
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}
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static uint64_t mailbox_reg_read(void *opaque, hwaddr offset, unsigned size)
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{
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CXLDeviceState *cxl_dstate;
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CXLCCI *cci = opaque;
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if (object_dynamic_cast(OBJECT(cci->intf), TYPE_CXL_TYPE3)) {
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cxl_dstate = &CXL_TYPE3(cci->intf)->cxl_dstate;
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} else if (object_dynamic_cast(OBJECT(cci->intf),
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TYPE_CXL_SWITCH_MAILBOX_CCI)) {
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cxl_dstate = &CXL_SWITCH_MAILBOX_CCI(cci->intf)->cxl_dstate;
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} else {
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return 0;
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}
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switch (size) {
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case 1:
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return cxl_dstate->mbox_reg_state[offset];
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case 2:
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return cxl_dstate->mbox_reg_state16[offset / size];
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case 4:
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return cxl_dstate->mbox_reg_state32[offset / size];
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case 8:
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if (offset == A_CXL_DEV_BG_CMD_STS) {
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uint64_t bg_status_reg;
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bg_status_reg = FIELD_DP64(0, CXL_DEV_BG_CMD_STS, OP,
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cci->bg.opcode);
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bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
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PERCENTAGE_COMP, cci->bg.complete_pct);
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bg_status_reg = FIELD_DP64(bg_status_reg, CXL_DEV_BG_CMD_STS,
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RET_CODE, cci->bg.ret_code);
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/* endian? */
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cxl_dstate->mbox_reg_state64[offset / size] = bg_status_reg;
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}
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if (offset == A_CXL_DEV_MAILBOX_STS) {
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uint64_t status_reg = cxl_dstate->mbox_reg_state64[offset / size];
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if (cci->bg.complete_pct) {
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status_reg = FIELD_DP64(status_reg, CXL_DEV_MAILBOX_STS, BG_OP,
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0);
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cxl_dstate->mbox_reg_state64[offset / size] = status_reg;
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}
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}
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return cxl_dstate->mbox_reg_state64[offset / size];
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default:
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g_assert_not_reached();
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}
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}
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static void mailbox_mem_writel(uint32_t *reg_state, hwaddr offset,
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uint64_t value)
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{
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switch (offset) {
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case A_CXL_DEV_MAILBOX_CTRL:
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/* fallthrough */
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case A_CXL_DEV_MAILBOX_CAP:
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/* RO register */
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break;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 32-bit access to 0x%" PRIx64 " (WI)\n",
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__func__, offset);
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return;
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}
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reg_state[offset / sizeof(*reg_state)] = value;
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}
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static void mailbox_mem_writeq(uint64_t *reg_state, hwaddr offset,
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uint64_t value)
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{
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switch (offset) {
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case A_CXL_DEV_MAILBOX_CMD:
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break;
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case A_CXL_DEV_BG_CMD_STS:
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break;
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case A_CXL_DEV_MAILBOX_STS:
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/* Read only register, will get updated by the state machine */
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return;
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default:
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qemu_log_mask(LOG_UNIMP,
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"%s Unexpected 64-bit access to 0x%" PRIx64 " (WI)\n",
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__func__, offset);
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return;
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}
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reg_state[offset / sizeof(*reg_state)] = value;
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}
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static void mailbox_reg_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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CXLDeviceState *cxl_dstate;
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CXLCCI *cci = opaque;
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if (object_dynamic_cast(OBJECT(cci->intf), TYPE_CXL_TYPE3)) {
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cxl_dstate = &CXL_TYPE3(cci->intf)->cxl_dstate;
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} else if (object_dynamic_cast(OBJECT(cci->intf),
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TYPE_CXL_SWITCH_MAILBOX_CCI)) {
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cxl_dstate = &CXL_SWITCH_MAILBOX_CCI(cci->intf)->cxl_dstate;
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} else {
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return;
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}
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if (offset >= A_CXL_DEV_CMD_PAYLOAD) {
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memcpy(cxl_dstate->mbox_reg_state + offset, &value, size);
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return;
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}
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switch (size) {
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case 4:
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mailbox_mem_writel(cxl_dstate->mbox_reg_state32, offset, value);
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break;
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case 8:
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mailbox_mem_writeq(cxl_dstate->mbox_reg_state64, offset, value);
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break;
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default:
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g_assert_not_reached();
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}
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if (ARRAY_FIELD_EX32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
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DOORBELL)) {
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uint64_t command_reg =
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cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD];
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uint8_t cmd_set = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD,
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COMMAND_SET);
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uint8_t cmd = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, COMMAND);
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size_t len_in = FIELD_EX64(command_reg, CXL_DEV_MAILBOX_CMD, LENGTH);
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uint8_t *pl = cxl_dstate->mbox_reg_state + A_CXL_DEV_CMD_PAYLOAD;
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/*
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* Copy taken to avoid need for individual command handlers to care
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* about aliasing.
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*/
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g_autofree uint8_t *pl_in_copy = NULL;
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size_t len_out = 0;
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uint64_t status_reg;
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bool bg_started = false;
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int rc;
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pl_in_copy = g_memdup2(pl, len_in);
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if (len_in == 0 || pl_in_copy) {
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/* Avoid stale data - including from earlier cmds */
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memset(pl, 0, CXL_MAILBOX_MAX_PAYLOAD_SIZE);
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rc = cxl_process_cci_message(cci, cmd_set, cmd, len_in, pl_in_copy,
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&len_out, pl, &bg_started);
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} else {
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rc = CXL_MBOX_INTERNAL_ERROR;
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}
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/* Set bg and the return code */
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status_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_STS, BG_OP,
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bg_started ? 1 : 0);
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status_reg = FIELD_DP64(status_reg, CXL_DEV_MAILBOX_STS, ERRNO, rc);
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/* Set the return length */
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command_reg = FIELD_DP64(0, CXL_DEV_MAILBOX_CMD, COMMAND_SET, cmd_set);
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command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD,
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COMMAND, cmd);
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command_reg = FIELD_DP64(command_reg, CXL_DEV_MAILBOX_CMD,
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LENGTH, len_out);
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cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_CMD] = command_reg;
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cxl_dstate->mbox_reg_state64[R_CXL_DEV_MAILBOX_STS] = status_reg;
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/* Tell the host we're done */
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CTRL,
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DOORBELL, 0);
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}
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}
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static uint64_t mdev_reg_read(void *opaque, hwaddr offset, unsigned size)
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{
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CXLDeviceState *cxl_dstate = opaque;
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return cxl_dstate->memdev_status;
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}
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static void ro_reg_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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/* Many register sets are read only */
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}
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static const MemoryRegionOps mdev_ops = {
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.read = mdev_reg_read,
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.write = ro_reg_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 8,
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.max_access_size = 8,
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},
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};
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static const MemoryRegionOps mailbox_ops = {
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.read = mailbox_reg_read,
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.write = mailbox_reg_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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static const MemoryRegionOps dev_ops = {
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.read = dev_reg_read,
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.write = ro_reg_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 1,
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.max_access_size = 8,
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},
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};
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static const MemoryRegionOps caps_ops = {
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.read = caps_reg_read,
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.write = ro_reg_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 8,
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.unaligned = false,
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},
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.impl = {
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.min_access_size = 4,
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.max_access_size = 8,
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},
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};
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void cxl_device_register_block_init(Object *obj, CXLDeviceState *cxl_dstate,
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CXLCCI *cci)
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{
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/* This will be a BAR, so needs to be rounded up to pow2 for PCI spec */
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memory_region_init(&cxl_dstate->device_registers, obj, "device-registers",
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pow2ceil(CXL_MMIO_SIZE));
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memory_region_init_io(&cxl_dstate->caps, obj, &caps_ops, cxl_dstate,
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"cap-array", CXL_CAPS_SIZE);
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memory_region_init_io(&cxl_dstate->device, obj, &dev_ops, cxl_dstate,
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"device-status", CXL_DEVICE_STATUS_REGISTERS_LENGTH);
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memory_region_init_io(&cxl_dstate->mailbox, obj, &mailbox_ops, cci,
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"mailbox", CXL_MAILBOX_REGISTERS_LENGTH);
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memory_region_init_io(&cxl_dstate->memory_device, obj, &mdev_ops,
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cxl_dstate, "memory device caps",
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CXL_MEMORY_DEVICE_REGISTERS_LENGTH);
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memory_region_add_subregion(&cxl_dstate->device_registers, 0,
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&cxl_dstate->caps);
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memory_region_add_subregion(&cxl_dstate->device_registers,
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CXL_DEVICE_STATUS_REGISTERS_OFFSET,
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&cxl_dstate->device);
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memory_region_add_subregion(&cxl_dstate->device_registers,
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CXL_MAILBOX_REGISTERS_OFFSET,
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&cxl_dstate->mailbox);
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memory_region_add_subregion(&cxl_dstate->device_registers,
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CXL_MEMORY_DEVICE_REGISTERS_OFFSET,
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&cxl_dstate->memory_device);
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}
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void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type,
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bool available)
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{
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if (available) {
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cxl_dstate->event_status |= (1 << log_type);
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} else {
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cxl_dstate->event_status &= ~(1 << log_type);
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}
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ARRAY_FIELD_DP64(cxl_dstate->dev_reg_state64, CXL_DEV_EVENT_STATUS,
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EVENT_STATUS, cxl_dstate->event_status);
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}
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static void device_reg_init_common(CXLDeviceState *cxl_dstate)
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{
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CXLEventLogType log;
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for (log = 0; log < CXL_EVENT_TYPE_MAX; log++) {
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cxl_event_set_status(cxl_dstate, log, false);
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}
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}
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static void mailbox_reg_init_common(CXLDeviceState *cxl_dstate)
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{
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const uint8_t msi_n = 9;
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/* 2048 payload size */
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
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PAYLOAD_SIZE, CXL_MAILBOX_PAYLOAD_SHIFT);
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cxl_dstate->payload_size = CXL_MAILBOX_MAX_PAYLOAD_SIZE;
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/* irq support */
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
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BG_INT_CAP, 1);
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
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MSI_N, msi_n);
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cxl_dstate->mbox_msi_n = msi_n;
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
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MBOX_READY_TIME, 0); /* Not reported */
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ARRAY_FIELD_DP32(cxl_dstate->mbox_reg_state32, CXL_DEV_MAILBOX_CAP,
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TYPE, 0); /* Inferred from class code */
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}
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static void memdev_reg_init_common(CXLDeviceState *cxl_dstate)
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{
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uint64_t memdev_status_reg;
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memdev_status_reg = FIELD_DP64(0, CXL_MEM_DEV_STS, MEDIA_STATUS, 1);
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memdev_status_reg = FIELD_DP64(memdev_status_reg, CXL_MEM_DEV_STS,
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MBOX_READY, 1);
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cxl_dstate->memdev_status = memdev_status_reg;
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}
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void cxl_device_register_init_t3(CXLType3Dev *ct3d)
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{
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CXLDeviceState *cxl_dstate = &ct3d->cxl_dstate;
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uint64_t *cap_h = cxl_dstate->caps_reg_state64;
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const int cap_count = 3;
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/* CXL Device Capabilities Array Register */
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ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_ID, 0);
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ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1);
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ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_COUNT, cap_count);
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cxl_device_cap_init(cxl_dstate, DEVICE_STATUS, 1,
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CXL_DEVICE_STATUS_VERSION);
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device_reg_init_common(cxl_dstate);
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cxl_device_cap_init(cxl_dstate, MAILBOX, 2, CXL_DEV_MAILBOX_VERSION);
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mailbox_reg_init_common(cxl_dstate);
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cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000,
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CXL_MEM_DEV_STATUS_VERSION);
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memdev_reg_init_common(cxl_dstate);
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cxl_initialize_mailbox_t3(&ct3d->cci, DEVICE(ct3d),
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CXL_MAILBOX_MAX_PAYLOAD_SIZE);
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}
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void cxl_device_register_init_swcci(CSWMBCCIDev *sw)
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{
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CXLDeviceState *cxl_dstate = &sw->cxl_dstate;
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uint64_t *cap_h = cxl_dstate->caps_reg_state64;
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const int cap_count = 3;
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/* CXL Device Capabilities Array Register */
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ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_ID, 0);
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ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_VERSION, 1);
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ARRAY_FIELD_DP64(cap_h, CXL_DEV_CAP_ARRAY, CAP_COUNT, cap_count);
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cxl_device_cap_init(cxl_dstate, DEVICE_STATUS, 1, 2);
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device_reg_init_common(cxl_dstate);
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cxl_device_cap_init(cxl_dstate, MAILBOX, 2, 1);
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mailbox_reg_init_common(cxl_dstate);
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cxl_device_cap_init(cxl_dstate, MEMORY_DEVICE, 0x4000, 1);
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memdev_reg_init_common(cxl_dstate);
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}
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uint64_t cxl_device_get_timestamp(CXLDeviceState *cxl_dstate)
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{
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uint64_t time, delta;
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uint64_t final_time = 0;
|
|
|
|
if (cxl_dstate->timestamp.set) {
|
|
/* Find the delta from the last time the host set the time. */
|
|
time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
|
|
delta = time - cxl_dstate->timestamp.last_set;
|
|
final_time = cxl_dstate->timestamp.host_set + delta;
|
|
}
|
|
|
|
return final_time;
|
|
}
|