qemu/hw/arm/strongarm.h
Thomas Huth fcf5ef2ab5 Move target-* CPU file into a target/ folder
We've currently got 18 architectures in QEMU, and thus 18 target-xxx
folders in the root folder of the QEMU source tree. More architectures
(e.g. RISC-V, AVR) are likely to be included soon, too, so the main
folder of the QEMU sources slowly gets quite overcrowded with the
target-xxx folders.
To disburden the main folder a little bit, let's move the target-xxx
folders into a dedicated target/ folder, so that target-xxx/ simply
becomes target/xxx/ instead.

Acked-by: Laurent Vivier <laurent@vivier.eu> [m68k part]
Acked-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> [tricore part]
Acked-by: Michael Walle <michael@walle.cc> [lm32 part]
Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> [s390x part]
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> [s390x part]
Acked-by: Eduardo Habkost <ehabkost@redhat.com> [i386 part]
Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> [sparc part]
Acked-by: Richard Henderson <rth@twiddle.net> [alpha part]
Acked-by: Max Filippov <jcmvbkbc@gmail.com> [xtensa part]
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ppc part]
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> [cris&microblaze part]
Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> [unicore32 part]
Signed-off-by: Thomas Huth <thuth@redhat.com>
2016-12-20 21:52:12 +01:00

70 lines
1.5 KiB
C

#ifndef STRONGARM_H
#define STRONGARM_H
#include "exec/memory.h"
#include "target/arm/cpu-qom.h"
#define SA_CS0 0x00000000
#define SA_CS1 0x08000000
#define SA_CS2 0x10000000
#define SA_CS3 0x18000000
#define SA_PCMCIA_CS0 0x20000000
#define SA_PCMCIA_CS1 0x30000000
#define SA_CS4 0x40000000
#define SA_CS5 0x48000000
/* system registers here */
#define SA_SDCS0 0xc0000000
#define SA_SDCS1 0xc8000000
#define SA_SDCS2 0xd0000000
#define SA_SDCS3 0xd8000000
enum {
SA_PIC_GPIO0_EDGE = 0,
SA_PIC_GPIO1_EDGE,
SA_PIC_GPIO2_EDGE,
SA_PIC_GPIO3_EDGE,
SA_PIC_GPIO4_EDGE,
SA_PIC_GPIO5_EDGE,
SA_PIC_GPIO6_EDGE,
SA_PIC_GPIO7_EDGE,
SA_PIC_GPIO8_EDGE,
SA_PIC_GPIO9_EDGE,
SA_PIC_GPIO10_EDGE,
SA_PIC_GPIOX_EDGE,
SA_PIC_LCD,
SA_PIC_UDC,
SA_PIC_RSVD1,
SA_PIC_UART1,
SA_PIC_UART2,
SA_PIC_UART3,
SA_PIC_MCP,
SA_PIC_SSP,
SA_PIC_DMA_CH0,
SA_PIC_DMA_CH1,
SA_PIC_DMA_CH2,
SA_PIC_DMA_CH3,
SA_PIC_DMA_CH4,
SA_PIC_DMA_CH5,
SA_PIC_OSTC0,
SA_PIC_OSTC1,
SA_PIC_OSTC2,
SA_PIC_OSTC3,
SA_PIC_RTC_HZ,
SA_PIC_RTC_ALARM,
};
typedef struct {
ARMCPU *cpu;
MemoryRegion sdram;
DeviceState *pic;
DeviceState *gpio;
DeviceState *ppc;
DeviceState *ssp;
SSIBus *ssp_bus;
} StrongARMState;
StrongARMState *sa1110_init(MemoryRegion *sysmem,
unsigned int sdram_size, const char *rev);
#endif