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Add the register definitions for the virtual interface of the GICv2. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-7-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
168 lines
6.1 KiB
C
168 lines
6.1 KiB
C
/*
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* ARM GIC support - internal interfaces
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*
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* Copyright (c) 2012 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef QEMU_ARM_GIC_INTERNAL_H
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#define QEMU_ARM_GIC_INTERNAL_H
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#include "hw/registerfields.h"
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#include "hw/intc/arm_gic.h"
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#define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
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#define GIC_BASE_IRQ 0
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#define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm))
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#define GIC_DIST_CLEAR_ENABLED(irq, cm) (s->irq_state[irq].enabled &= ~(cm))
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#define GIC_DIST_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
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#define GIC_DIST_SET_PENDING(irq, cm) (s->irq_state[irq].pending |= (cm))
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#define GIC_DIST_CLEAR_PENDING(irq, cm) (s->irq_state[irq].pending &= ~(cm))
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#define GIC_DIST_SET_ACTIVE(irq, cm) (s->irq_state[irq].active |= (cm))
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#define GIC_DIST_CLEAR_ACTIVE(irq, cm) (s->irq_state[irq].active &= ~(cm))
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#define GIC_DIST_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
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#define GIC_DIST_SET_MODEL(irq) (s->irq_state[irq].model = true)
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#define GIC_DIST_CLEAR_MODEL(irq) (s->irq_state[irq].model = false)
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#define GIC_DIST_TEST_MODEL(irq) (s->irq_state[irq].model)
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#define GIC_DIST_SET_LEVEL(irq, cm) (s->irq_state[irq].level |= (cm))
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#define GIC_DIST_CLEAR_LEVEL(irq, cm) (s->irq_state[irq].level &= ~(cm))
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#define GIC_DIST_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
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#define GIC_DIST_SET_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger = true)
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#define GIC_DIST_CLEAR_EDGE_TRIGGER(irq) \
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(s->irq_state[irq].edge_trigger = false)
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#define GIC_DIST_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger)
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#define GIC_DIST_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
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s->priority1[irq][cpu] : \
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s->priority2[(irq) - GIC_INTERNAL])
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#define GIC_DIST_TARGET(irq) (s->irq_target[irq])
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#define GIC_DIST_CLEAR_GROUP(irq, cm) (s->irq_state[irq].group &= ~(cm))
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#define GIC_DIST_SET_GROUP(irq, cm) (s->irq_state[irq].group |= (cm))
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#define GIC_DIST_TEST_GROUP(irq, cm) ((s->irq_state[irq].group & (cm)) != 0)
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#define GICD_CTLR_EN_GRP0 (1U << 0)
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#define GICD_CTLR_EN_GRP1 (1U << 1)
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#define GICC_CTLR_EN_GRP0 (1U << 0)
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#define GICC_CTLR_EN_GRP1 (1U << 1)
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#define GICC_CTLR_ACK_CTL (1U << 2)
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#define GICC_CTLR_FIQ_EN (1U << 3)
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#define GICC_CTLR_CBPR (1U << 4) /* GICv1: SBPR */
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#define GICC_CTLR_EOIMODE (1U << 9)
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#define GICC_CTLR_EOIMODE_NS (1U << 10)
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REG32(GICH_HCR, 0x0)
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FIELD(GICH_HCR, EN, 0, 1)
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FIELD(GICH_HCR, UIE, 1, 1)
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FIELD(GICH_HCR, LRENPIE, 2, 1)
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FIELD(GICH_HCR, NPIE, 3, 1)
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FIELD(GICH_HCR, VGRP0EIE, 4, 1)
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FIELD(GICH_HCR, VGRP0DIE, 5, 1)
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FIELD(GICH_HCR, VGRP1EIE, 6, 1)
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FIELD(GICH_HCR, VGRP1DIE, 7, 1)
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FIELD(GICH_HCR, EOICount, 27, 5)
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#define GICH_HCR_MASK \
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(R_GICH_HCR_EN_MASK | R_GICH_HCR_UIE_MASK | \
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R_GICH_HCR_LRENPIE_MASK | R_GICH_HCR_NPIE_MASK | \
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R_GICH_HCR_VGRP0EIE_MASK | R_GICH_HCR_VGRP0DIE_MASK | \
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R_GICH_HCR_VGRP1EIE_MASK | R_GICH_HCR_VGRP1DIE_MASK | \
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R_GICH_HCR_EOICount_MASK)
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REG32(GICH_VTR, 0x4)
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FIELD(GICH_VTR, ListRegs, 0, 6)
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FIELD(GICH_VTR, PREbits, 26, 3)
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FIELD(GICH_VTR, PRIbits, 29, 3)
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REG32(GICH_VMCR, 0x8)
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FIELD(GICH_VMCR, VMCCtlr, 0, 10)
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FIELD(GICH_VMCR, VMABP, 18, 3)
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FIELD(GICH_VMCR, VMBP, 21, 3)
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FIELD(GICH_VMCR, VMPriMask, 27, 5)
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REG32(GICH_MISR, 0x10)
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FIELD(GICH_MISR, EOI, 0, 1)
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FIELD(GICH_MISR, U, 1, 1)
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FIELD(GICH_MISR, LRENP, 2, 1)
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FIELD(GICH_MISR, NP, 3, 1)
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FIELD(GICH_MISR, VGrp0E, 4, 1)
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FIELD(GICH_MISR, VGrp0D, 5, 1)
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FIELD(GICH_MISR, VGrp1E, 6, 1)
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FIELD(GICH_MISR, VGrp1D, 7, 1)
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REG32(GICH_EISR0, 0x20)
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REG32(GICH_EISR1, 0x24)
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REG32(GICH_ELRSR0, 0x30)
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REG32(GICH_ELRSR1, 0x34)
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REG32(GICH_APR, 0xf0)
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REG32(GICH_LR0, 0x100)
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FIELD(GICH_LR0, VirtualID, 0, 10)
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FIELD(GICH_LR0, PhysicalID, 10, 10)
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FIELD(GICH_LR0, CPUID, 10, 3)
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FIELD(GICH_LR0, EOI, 19, 1)
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FIELD(GICH_LR0, Priority, 23, 5)
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FIELD(GICH_LR0, State, 28, 2)
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FIELD(GICH_LR0, Grp1, 30, 1)
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FIELD(GICH_LR0, HW, 31, 1)
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/* Last LR register */
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REG32(GICH_LR63, 0x1fc)
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#define GICH_LR_MASK \
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(R_GICH_LR0_VirtualID_MASK | R_GICH_LR0_PhysicalID_MASK | \
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R_GICH_LR0_CPUID_MASK | R_GICH_LR0_EOI_MASK | \
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R_GICH_LR0_Priority_MASK | R_GICH_LR0_State_MASK | \
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R_GICH_LR0_Grp1_MASK | R_GICH_LR0_HW_MASK)
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/* Valid bits for GICC_CTLR for GICv1, v1 with security extensions,
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* GICv2 and GICv2 with security extensions:
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*/
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#define GICC_CTLR_V1_MASK 0x1
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#define GICC_CTLR_V1_S_MASK 0x1f
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#define GICC_CTLR_V2_MASK 0x21f
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#define GICC_CTLR_V2_S_MASK 0x61f
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/* The special cases for the revision property: */
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#define REV_11MPCORE 0
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uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
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void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
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MemTxAttrs attrs);
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static inline bool gic_test_pending(GICState *s, int irq, int cm)
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{
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if (s->revision == REV_11MPCORE) {
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return s->irq_state[irq].pending & cm;
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} else {
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/* Edge-triggered interrupts are marked pending on a rising edge, but
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* level-triggered interrupts are either considered pending when the
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* level is active or if software has explicitly written to
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* GICD_ISPENDR to set the state pending.
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*/
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return (s->irq_state[irq].pending & cm) ||
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(!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_LEVEL(irq, cm));
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}
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}
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static inline bool gic_is_vcpu(int cpu)
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{
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return cpu >= GIC_NCPU;
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}
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#endif /* QEMU_ARM_GIC_INTERNAL_H */
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