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![]() This fixes a bug in the disassembler constraints used to lift instructions into pseudo-instructions, whereby addiw instructions are always lifted to sext.w instead of just lifting addiw with a zero immediate. An associated fix has been made to the metadata used to machine generate the disseasembler: https://github.com/michaeljclark/riscv-meta/ commit/4a6b2f3898430768acfe201405224d2ea31e1477 Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
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.. | ||
libvixl | ||
alpha.c | ||
arm-a64.cc | ||
arm.c | ||
cris.c | ||
hppa.c | ||
i386.c | ||
lm32.c | ||
m68k.c | ||
Makefile.objs | ||
microblaze.c | ||
mips.c | ||
moxie.c | ||
nios2.c | ||
ppc.c | ||
riscv.c | ||
s390.c | ||
sh4.c | ||
sparc.c | ||
tci.c | ||
xtensa.c |