qemu/hw/riscv
Alistair Francis 3ef6434409 hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer
Connect the Ibex timer to the OpenTitan machine. The timer can trigger
the RISC-V MIE interrupt as well as a custom device interrupt.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 5e7f4e9b4537f863bcb8db1264b840b56ef2a929.1624001156.git.alistair.francis@wdc.com
2021-06-24 05:00:13 -07:00
..
boot.c riscv: Pass RISCVHartArrayState by pointer 2021-01-16 14:34:46 -08:00
Kconfig hw/riscv: Enable VIRTIO_VGA for RISC-V virt machine 2021-05-11 20:02:06 +10:00
meson.build riscv: Add initial support for Shakti C machine 2021-05-11 20:01:38 +10:00
microchip_pfsoc.c hw/riscv: microchip_pfsoc: Support direct kernel boot 2021-06-08 09:59:42 +10:00
numa.c hw: Do not include qemu/log.h if it is not necessary 2021-05-02 17:24:50 +02:00
opentitan.c hw/riscv: OpenTitan: Connect the mtime and mtimecmp timer 2021-06-24 05:00:13 -07:00
riscv_hart.c hw/riscv: hart: Add a new 'resetvec' property 2020-09-09 15:54:18 -07:00
shakti_c.c hw/riscv: Connect Shakti UART to Shakti platform 2021-05-11 20:02:06 +10:00
sifive_e.c hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[] 2021-05-11 20:01:10 +10:00
sifive_u.c hw/riscv: Use macros for BIOS image names 2021-06-08 09:59:42 +10:00
spike.c hw/riscv: Use macros for BIOS image names 2021-06-08 09:59:42 +10:00
virt.c hw/riscv: Use macros for BIOS image names 2021-06-08 09:59:42 +10:00