qemu/target-arm
Paul Brook d4c430a80f Large page TLB flush
QEMU uses a fixed page size for the CPU TLB.  If the guest uses large
pages then we effectively split these into multiple smaller pages, and
populate the corresponding TLB entries on demand.

When the guest invalidates the TLB by virtual address we must invalidate
all entries covered by the large page.  However the address used to
invalidate the entry may not be present in the QEMU TLB, so we do not
know which regions to clear.

Implementing a full vaiable size TLB is hard and slow, so just keep a
simple address/mask pair to record which addresses may have been mapped by
large pages.  If the guest invalidates this region then flush the
whole TLB.

Signed-off-by: Paul Brook <paul@codesourcery.com>
2010-03-17 02:44:41 +00:00
..
cpu.h Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h. 2010-03-12 16:28:24 +00:00
exec.h kill regs_to_env and env_to_regs 2010-01-19 16:31:02 -06:00
helper.c Large page TLB flush 2010-03-17 02:44:41 +00:00
helpers.h ARM atomic ops rewrite 2009-11-22 21:35:13 +00:00
iwmmxt_helper.c Update to a hopefully more future proof FSF address 2009-07-16 20:47:01 +00:00
machine.c Save/restore ARMv6 MMU state 2009-07-31 13:19:39 +01:00
neon_helper.c target-arm: fix neon shift helper functions 2009-10-27 09:46:26 +01:00
op_addsub.h TCG variable type checking. 2008-11-17 14:43:54 +00:00
op_helper.c target-arm: use native tcg-ops for ror/bic/vorn 2009-10-27 09:46:27 +01:00
translate.c target-arm: make RFE usable with any register 2010-03-13 12:01:29 +01:00