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![Richard Henderson](/assets/img/avatar_default.png)
This is the cpu side of the operation. Register one irq line, called EIC. Split out the rather different processing to a separate function. Delay initialization of gpio irqs until realize. We need to provide a window after init in which the board can set eic_present. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220421151735.31996-57-richard.henderson@linaro.org>
390 lines
10 KiB
C
390 lines
10 KiB
C
/*
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* QEMU Nios II CPU
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qemu/module.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "exec/log.h"
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#include "exec/gdbstub.h"
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#include "hw/qdev-properties.h"
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static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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env->pc = value;
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}
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static bool nios2_cpu_has_work(CPUState *cs)
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{
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return cs->interrupt_request & CPU_INTERRUPT_HARD;
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}
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static void nios2_cpu_reset(DeviceState *dev)
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{
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CPUState *cs = CPU(dev);
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Nios2CPU *cpu = NIOS2_CPU(cs);
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Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(cpu);
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CPUNios2State *env = &cpu->env;
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ncc->parent_reset(dev);
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memset(env->ctrl, 0, sizeof(env->ctrl));
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env->pc = cpu->reset_addr;
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#if defined(CONFIG_USER_ONLY)
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/* Start in user mode with interrupts enabled. */
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env->ctrl[CR_STATUS] = CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE;
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memset(env->regs, 0, sizeof(env->regs));
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#else
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env->ctrl[CR_STATUS] = CR_STATUS_RSIE;
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nios2_update_crs(env);
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memset(env->shadow_regs, 0, sizeof(env->shadow_regs));
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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static void eic_set_irq(void *opaque, int irq, int level)
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{
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Nios2CPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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if (level) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static void iic_set_irq(void *opaque, int irq, int level)
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{
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Nios2CPU *cpu = opaque;
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CPUNios2State *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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env->ctrl[CR_IPENDING] = deposit32(env->ctrl[CR_IPENDING], irq, 1, !!level);
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if (env->ctrl[CR_IPENDING]) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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#endif
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static void nios2_cpu_initfn(Object *obj)
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{
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Nios2CPU *cpu = NIOS2_CPU(obj);
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cpu_set_cpustate_pointers(cpu);
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#if !defined(CONFIG_USER_ONLY)
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mmu_init(&cpu->env);
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#endif
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}
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static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
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{
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return object_class_by_name(TYPE_NIOS2_CPU);
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}
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static void realize_cr_status(CPUState *cs)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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/* Begin with all fields of all registers are reserved. */
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memset(cpu->cr_state, 0, sizeof(cpu->cr_state));
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/*
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* The combination of writable and readonly is the set of all
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* non-reserved fields. We apply writable as a mask to bits,
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* and merge in existing readonly bits, before storing.
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*/
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#define WR_REG(C) cpu->cr_state[C].writable = -1
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#define RO_REG(C) cpu->cr_state[C].readonly = -1
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#define WR_FIELD(C, F) cpu->cr_state[C].writable |= R_##C##_##F##_MASK
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#define RO_FIELD(C, F) cpu->cr_state[C].readonly |= R_##C##_##F##_MASK
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WR_FIELD(CR_STATUS, PIE);
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WR_REG(CR_ESTATUS);
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WR_REG(CR_BSTATUS);
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RO_REG(CR_CPUID);
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RO_REG(CR_EXCEPTION);
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WR_REG(CR_BADADDR);
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if (cpu->eic_present) {
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WR_FIELD(CR_STATUS, RSIE);
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RO_FIELD(CR_STATUS, NMI);
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WR_FIELD(CR_STATUS, PRS);
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RO_FIELD(CR_STATUS, CRS);
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WR_FIELD(CR_STATUS, IL);
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WR_FIELD(CR_STATUS, IH);
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} else {
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RO_FIELD(CR_STATUS, RSIE);
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WR_REG(CR_IENABLE);
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RO_REG(CR_IPENDING);
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}
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if (cpu->mmu_present) {
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WR_FIELD(CR_STATUS, U);
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WR_FIELD(CR_STATUS, EH);
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WR_FIELD(CR_PTEADDR, VPN);
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WR_FIELD(CR_PTEADDR, PTBASE);
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RO_FIELD(CR_TLBMISC, D);
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RO_FIELD(CR_TLBMISC, PERM);
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RO_FIELD(CR_TLBMISC, BAD);
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RO_FIELD(CR_TLBMISC, DBL);
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WR_FIELD(CR_TLBMISC, PID);
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WR_FIELD(CR_TLBMISC, WE);
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WR_FIELD(CR_TLBMISC, RD);
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WR_FIELD(CR_TLBMISC, WAY);
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WR_REG(CR_TLBACC);
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}
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/*
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* TODO: ECC (config, eccinj) and MPU (config, mpubase, mpuacc) are
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* unimplemented, so their corresponding control regs remain reserved.
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*/
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#undef WR_REG
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#undef RO_REG
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#undef WR_FIELD
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#undef RO_FIELD
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}
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static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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Nios2CPU *cpu = NIOS2_CPU(cs);
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Nios2CPUClass *ncc = NIOS2_CPU_GET_CLASS(dev);
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Error *local_err = NULL;
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#ifndef CONFIG_USER_ONLY
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if (cpu->eic_present) {
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qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1);
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} else {
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qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32);
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}
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#endif
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cpu_exec_realizefn(cs, &local_err);
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if (local_err != NULL) {
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error_propagate(errp, local_err);
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return;
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}
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realize_cr_status(cs);
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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/* We have reserved storage for cpuid; might as well use it. */
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cpu->env.ctrl[CR_CPUID] = cs->cpu_index;
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ncc->parent_realize(dev, errp);
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}
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#ifndef CONFIG_USER_ONLY
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static bool eic_take_interrupt(Nios2CPU *cpu)
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{
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CPUNios2State *env = &cpu->env;
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const uint32_t status = env->ctrl[CR_STATUS];
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if (cpu->rnmi) {
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return !(status & CR_STATUS_NMI);
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}
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if (!(status & CR_STATUS_PIE)) {
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return false;
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}
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if (cpu->ril <= FIELD_EX32(status, CR_STATUS, IL)) {
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return false;
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}
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if (cpu->rrs != FIELD_EX32(status, CR_STATUS, CRS)) {
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return true;
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}
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return status & CR_STATUS_RSIE;
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}
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static bool iic_take_interrupt(Nios2CPU *cpu)
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{
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CPUNios2State *env = &cpu->env;
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if (!(env->ctrl[CR_STATUS] & CR_STATUS_PIE)) {
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return false;
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}
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return env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE];
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}
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static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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if (cpu->eic_present
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? eic_take_interrupt(cpu)
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: iic_take_interrupt(cpu)) {
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cs->exception_index = EXCP_IRQ;
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nios2_cpu_do_interrupt(cs);
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return true;
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}
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}
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return false;
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}
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#endif /* !CONFIG_USER_ONLY */
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static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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{
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/* NOTE: NiosII R2 is not supported yet. */
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info->mach = bfd_arch_nios2;
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info->print_insn = print_insn_nios2;
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}
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static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUNios2State *env = &cpu->env;
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uint32_t val;
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if (n < 32) { /* GP regs */
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val = env->regs[n];
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} else if (n == 32) { /* PC */
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val = env->pc;
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} else if (n < 49) { /* Status regs */
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unsigned cr = n - 33;
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if (nios2_cr_reserved(&cpu->cr_state[cr])) {
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val = 0;
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} else {
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val = env->ctrl[n - 33];
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}
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} else {
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/* Invalid regs */
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return 0;
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}
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return gdb_get_reg32(mem_buf, val);
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}
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static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUNios2State *env = &cpu->env;
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uint32_t val;
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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val = ldl_p(mem_buf);
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if (n < 32) { /* GP regs */
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env->regs[n] = val;
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} else if (n == 32) { /* PC */
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env->pc = val;
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} else if (n < 49) { /* Status regs */
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unsigned cr = n - 33;
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/* ??? Maybe allow the debugger to write to readonly fields. */
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val &= cpu->cr_state[cr].writable;
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val |= cpu->cr_state[cr].readonly & env->ctrl[cr];
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env->ctrl[cr] = val;
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} else {
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g_assert_not_reached();
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}
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return 4;
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}
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static Property nios2_properties[] = {
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DEFINE_PROP_BOOL("diverr_present", Nios2CPU, diverr_present, true),
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DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true),
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/* ALTR,pid-num-bits */
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DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8),
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/* ALTR,tlb-num-ways */
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DEFINE_PROP_UINT32("mmu_tlb_num_ways", Nios2CPU, tlb_num_ways, 16),
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/* ALTR,tlb-num-entries */
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DEFINE_PROP_UINT32("mmu_pid_num_entries", Nios2CPU, tlb_num_entries, 256),
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DEFINE_PROP_END_OF_LIST(),
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};
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#ifndef CONFIG_USER_ONLY
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#include "hw/core/sysemu-cpu-ops.h"
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static const struct SysemuCPUOps nios2_sysemu_ops = {
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.get_phys_page_debug = nios2_cpu_get_phys_page_debug,
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};
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#endif
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#include "hw/core/tcg-cpu-ops.h"
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static const struct TCGCPUOps nios2_tcg_ops = {
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.initialize = nios2_tcg_init,
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#ifndef CONFIG_USER_ONLY
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.tlb_fill = nios2_cpu_tlb_fill,
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.cpu_exec_interrupt = nios2_cpu_exec_interrupt,
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.do_interrupt = nios2_cpu_do_interrupt,
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.do_unaligned_access = nios2_cpu_do_unaligned_access,
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#endif /* !CONFIG_USER_ONLY */
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};
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static void nios2_cpu_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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Nios2CPUClass *ncc = NIOS2_CPU_CLASS(oc);
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device_class_set_parent_realize(dc, nios2_cpu_realizefn,
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&ncc->parent_realize);
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device_class_set_props(dc, nios2_properties);
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device_class_set_parent_reset(dc, nios2_cpu_reset, &ncc->parent_reset);
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cc->class_by_name = nios2_cpu_class_by_name;
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cc->has_work = nios2_cpu_has_work;
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cc->dump_state = nios2_cpu_dump_state;
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cc->set_pc = nios2_cpu_set_pc;
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cc->disas_set_info = nios2_cpu_disas_set_info;
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#ifndef CONFIG_USER_ONLY
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cc->sysemu_ops = &nios2_sysemu_ops;
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#endif
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cc->gdb_read_register = nios2_cpu_gdb_read_register;
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cc->gdb_write_register = nios2_cpu_gdb_write_register;
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cc->gdb_num_core_regs = 49;
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cc->tcg_ops = &nios2_tcg_ops;
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}
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static const TypeInfo nios2_cpu_type_info = {
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.name = TYPE_NIOS2_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(Nios2CPU),
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.instance_init = nios2_cpu_initfn,
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.class_size = sizeof(Nios2CPUClass),
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.class_init = nios2_cpu_class_init,
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};
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static void nios2_cpu_register_types(void)
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{
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type_register_static(&nios2_cpu_type_info);
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}
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type_init(nios2_cpu_register_types)
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