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6ed924823c
For the ECSPIx_CONREG register BURST_LENGTH field, the manual says:
0x020 A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
0x021 A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
Current logic uses either s->burst_length or 32, whichever smaller,
to determine how many bits it should read from the tx fifo each time.
For example, for a 48 bit burst length, current logic transfers the
first 32 bit from the first word in the tx fifo, followed by a 16
bit from the second word in the tx fifo, which is wrong. The correct
logic should be: transfer the first 16 bit from the first word in
the tx fifo, followed by a 32 bit from the second word in the tx fifo.
With this change, SPI flash can be successfully probed by U-Boot on
imx6 sabrelite board.
=> sf probe
SF: Detected sst25vf016b with page size 256 Bytes, erase size 4 KiB, total 2 MiB
Fixes:
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|---|---|---|
| .. | ||
| aspeed_smc.c | ||
| imx_spi.c | ||
| Kconfig | ||
| meson.build | ||
| mss-spi.c | ||
| npcm7xx_fiu.c | ||
| omap_spi.c | ||
| pl022.c | ||
| ssi.c | ||
| stm32f2xx_spi.c | ||
| trace-events | ||
| trace.h | ||
| xilinx_spi.c | ||
| xilinx_spips.c | ||