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qemu/target-arm
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Peter Crosthwaite f7838b5290 arm: cortex-a9: Fix cache-line size and associativity 
For A9, The cache associativity is 4 and the lines size is 32B.
Self identify in CCSIDR accordingly. Cache size remains at 16k.

QEMU doesn't emulate caches, but we should still report the correct
cache-line size to the guest. Some guests (like u-boot) complain if
the cache-line size mismatches a requested flush or invalidate
operation.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1de6bd40155a1d2f2e93e24b1b1d1d677a432641.1408346233.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-08-19 19:02:40 +01:00
..
arm-semi.c cpu: Move opaque field from CPU_COMMON to CPUState 2014-03-13 19:20:47 +01:00
arm_ldst.h softmmu: introduce cpu_ldst.h 2014-06-05 16:10:33 +02:00
cpu-qom.h target-arm: Adjust debug ID registers per-CPU 2014-08-19 19:02:03 +01:00
cpu.c arm: cortex-a9: Fix cache-line size and associativity 2014-08-19 19:02:40 +01:00
cpu.h target-arm: Implement ARMv8 single-stepping for AArch32 code 2014-08-19 19:02:03 +01:00
cpu64.c target-arm: Adjust debug ID registers per-CPU 2014-08-19 19:02:03 +01:00
crypto_helper.c target-arm: Use Common Tables in AES Instructions 2014-06-16 13:24:33 +02:00
gdbstub.c cpu: Introduce CPUClass::gdb_{read,write}_register() 2013-07-27 00:04:17 +02:00
gdbstub64.c target-arm/gdbstub64.c: remove useless 'break' statement. 2014-04-17 21:34:06 +01:00
helper-a64.c target-arm: Make far_el1 an array 2014-08-04 14:41:54 +01:00
helper-a64.h target-arm: A64: Implement CRC instructions 2014-06-09 16:06:12 +01:00
helper.c target-arm: Implement MDSCR_EL1 as having state 2014-08-19 19:02:03 +01:00
helper.h target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
internals.h target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
iwmmxt_helper.c target-arm: Delete unused iwmmxt_msadb helper 2014-06-09 16:06:12 +01:00
kvm-consts.h arm/virt: Use PSCI v0.2 function IDs in the DT when KVM uses PSCI v0.2 2014-08-19 19:02:25 +01:00
kvm-stub.c target-arm: Initialize cpreg list from KVM when using KVM 2013-06-25 18:16:10 +01:00
kvm.c target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
kvm32.c target-arm: Implement vCPU reset via KVM_ARM_VCPU_INIT for 32-bit CPUs 2014-07-08 13:05:11 +01:00
kvm64.c target-arm: A64: Break out aarch64_save/restore_sp 2014-08-04 14:41:54 +01:00
kvm_arm.h target-arm: Common kvm_arm_vcpu_init() for KVM ARM and KVM ARM64 2014-06-19 18:33:02 +01:00
machine.c target-arm: Add SPSR entries for EL2/HYP and EL3/MON 2014-05-27 17:09:52 +01:00
Makefile.objs target-arm: A64: add stubs for a64 specific helpers 2013-12-17 19:42:32 +00:00
neon_helper.c target-arm: add support for v8 VMULL.P64 instruction 2014-06-09 16:06:11 +01:00
op_addsub.h Correct spelling of licensed 2011-07-23 11:26:12 -05:00
op_helper.c target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
translate-a64.c target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00
translate.c target-arm: Implement ARMv8 single-stepping for AArch32 code 2014-08-19 19:02:03 +01:00
translate.h target-arm: Implement ARMv8 single-step handling for A64 code 2014-08-19 19:02:03 +01:00