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6e4e3ae936
CXL host bridges themselves may have MMIO. Since host bridges don't have a BAR they are treated as special for MMIO. This patch includes i386/pc support. Also hook up the device reset now that we have have the MMIO space in which the results are visible. Note that we duplicate the PCI express case for the aml_build but the implementations will diverge when the CXL specific _OSC is introduced. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Co-developed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-24-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
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| .. | ||
| cxl_root_port.c | ||
| dec.c | ||
| dec.h | ||
| gen_pcie_root_port.c | ||
| i82801b11.c | ||
| ioh3420.c | ||
| Kconfig | ||
| meson.build | ||
| pci_bridge_dev.c | ||
| pci_expander_bridge.c | ||
| pcie_pci_bridge.c | ||
| pcie_root_port.c | ||
| simba.c | ||
| xio3130_downstream.c | ||
| xio3130_upstream.c | ||