mirror of
https://gitlab.com/qemu-project/qemu
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eb37086fb0
These members will be used to help plugins to identify registers. The added members in instances of GDBFeature dynamically generated by CPUs will be filled in later changes. Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20231213-gdb-v17-10-777047380591@daynix.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240227144335.1196131-15-alex.bennee@linaro.org>
371 lines
10 KiB
C
371 lines
10 KiB
C
/*
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* RISC-V GDB Server Stub
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "exec/gdbstub.h"
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#include "gdbstub/helpers.h"
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#include "cpu.h"
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struct TypeSize {
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const char *gdb_type;
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const char *id;
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int size;
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const char suffix;
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};
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static const struct TypeSize vec_lanes[] = {
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/* quads */
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{ "uint128", "quads", 128, 'q' },
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/* 64 bit */
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{ "uint64", "longs", 64, 'l' },
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/* 32 bit */
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{ "uint32", "words", 32, 'w' },
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/* 16 bit */
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{ "uint16", "shorts", 16, 's' },
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/*
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* TODO: currently there is no reliable way of telling
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* if the remote gdb actually understands ieee_half so
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* we don't expose it in the target description for now.
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* { "ieee_half", 16, 'h', 'f' },
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*/
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/* bytes */
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{ "uint8", "bytes", 8, 'b' },
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};
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int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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target_ulong tmp;
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if (n < 32) {
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tmp = env->gpr[n];
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} else if (n == 32) {
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tmp = env->pc;
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} else {
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return 0;
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}
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switch (mcc->misa_mxl_max) {
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case MXL_RV32:
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return gdb_get_reg32(mem_buf, tmp);
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case MXL_RV64:
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case MXL_RV128:
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return gdb_get_reg64(mem_buf, tmp);
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default:
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g_assert_not_reached();
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}
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return 0;
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}
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int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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int length = 0;
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target_ulong tmp;
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switch (mcc->misa_mxl_max) {
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case MXL_RV32:
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tmp = (int32_t)ldl_p(mem_buf);
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length = 4;
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break;
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case MXL_RV64:
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case MXL_RV128:
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if (env->xl < MXL_RV64) {
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tmp = (int32_t)ldq_p(mem_buf);
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} else {
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tmp = ldq_p(mem_buf);
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}
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length = 8;
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break;
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default:
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g_assert_not_reached();
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}
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if (n > 0 && n < 32) {
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env->gpr[n] = tmp;
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} else if (n == 32) {
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env->pc = tmp;
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}
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return length;
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}
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static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n < 32) {
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if (env->misa_ext & RVD) {
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return gdb_get_reg64(buf, env->fpr[n]);
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}
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if (env->misa_ext & RVF) {
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return gdb_get_reg32(buf, env->fpr[n]);
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}
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}
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return 0;
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}
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static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n < 32) {
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env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */
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return sizeof(uint64_t);
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}
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return 0;
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}
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static int riscv_gdb_get_vector(CPUState *cs, GByteArray *buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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uint16_t vlenb = cpu->cfg.vlenb;
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if (n < 32) {
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int i;
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int cnt = 0;
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for (i = 0; i < vlenb; i += 8) {
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cnt += gdb_get_reg64(buf,
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env->vreg[(n * vlenb + i) / 8]);
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}
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return cnt;
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}
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return 0;
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}
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static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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uint16_t vlenb = cpu->cfg.vlenb;
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if (n < 32) {
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int i;
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for (i = 0; i < vlenb; i += 8) {
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env->vreg[(n * vlenb + i) / 8] = ldq_p(mem_buf + i);
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}
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return vlenb;
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}
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return 0;
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}
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static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n < CSR_TABLE_SIZE) {
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target_ulong val = 0;
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int result;
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result = riscv_csrrw_debug(env, n, &val, 0, 0);
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if (result == RISCV_EXCP_NONE) {
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return gdb_get_regl(buf, val);
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}
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}
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return 0;
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}
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static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (n < CSR_TABLE_SIZE) {
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target_ulong val = ldtul_p(mem_buf);
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int result;
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result = riscv_csrrw_debug(env, n, NULL, val, -1);
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if (result == RISCV_EXCP_NONE) {
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return sizeof(target_ulong);
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}
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}
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return 0;
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}
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static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n)
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{
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if (n == 0) {
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#ifdef CONFIG_USER_ONLY
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return gdb_get_regl(buf, 0);
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#else
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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return gdb_get_regl(buf, env->priv);
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#endif
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}
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return 0;
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}
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static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)
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{
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if (n == 0) {
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#ifndef CONFIG_USER_ONLY
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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env->priv = ldtul_p(mem_buf) & 0x3;
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if (env->priv == PRV_RESERVED) {
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env->priv = PRV_S;
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}
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#endif
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return sizeof(target_ulong);
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}
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return 0;
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}
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static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)
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{
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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GDBFeatureBuilder builder;
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riscv_csr_predicate_fn predicate;
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int bitsize = riscv_cpu_max_xlen(mcc);
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const char *name;
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int i;
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#if !defined(CONFIG_USER_ONLY)
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env->debugger = true;
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#endif
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/* Until gdb knows about 128-bit registers */
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if (bitsize > 64) {
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bitsize = 64;
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}
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gdb_feature_builder_init(&builder, &cpu->dyn_csr_feature,
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"org.gnu.gdb.riscv.csr", "riscv-csr.xml",
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base_reg);
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for (i = 0; i < CSR_TABLE_SIZE; i++) {
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if (env->priv_ver < csr_ops[i].min_priv_ver) {
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continue;
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}
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predicate = csr_ops[i].predicate;
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if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
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name = csr_ops[i].name;
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if (!name) {
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name = g_strdup_printf("csr%03x", i);
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}
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gdb_feature_builder_append_reg(&builder, name, bitsize, i,
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"int", NULL);
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}
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}
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gdb_feature_builder_end(&builder);
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#if !defined(CONFIG_USER_ONLY)
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env->debugger = false;
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#endif
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return &cpu->dyn_csr_feature;
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}
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static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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int reg_width = cpu->cfg.vlenb;
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GDBFeatureBuilder builder;
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int i;
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gdb_feature_builder_init(&builder, &cpu->dyn_vreg_feature,
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"org.gnu.gdb.riscv.vector", "riscv-vector.xml",
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base_reg);
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/* First define types and totals in a whole VL */
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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int count = reg_width / vec_lanes[i].size;
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gdb_feature_builder_append_tag(
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&builder, "<vector id=\"%s\" type=\"%s\" count=\"%d\"/>",
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vec_lanes[i].id, vec_lanes[i].gdb_type, count);
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}
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/* Define unions */
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gdb_feature_builder_append_tag(&builder, "<union id=\"riscv_vector\">");
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for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {
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gdb_feature_builder_append_tag(&builder,
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"<field name=\"%c\" type=\"%s\"/>",
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vec_lanes[i].suffix, vec_lanes[i].id);
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}
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gdb_feature_builder_append_tag(&builder, "</union>");
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/* Define vector registers */
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for (i = 0; i < 32; i++) {
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gdb_feature_builder_append_reg(&builder, g_strdup_printf("v%d", i),
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reg_width, i, "riscv_vector", "vector");
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}
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gdb_feature_builder_end(&builder);
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return &cpu->dyn_vreg_feature;
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}
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void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)
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{
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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if (env->misa_ext & RVD) {
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gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
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gdb_find_static_feature("riscv-64bit-fpu.xml"),
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0);
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} else if (env->misa_ext & RVF) {
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gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
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gdb_find_static_feature("riscv-32bit-fpu.xml"),
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0);
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}
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if (env->misa_ext & RVV) {
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gdb_register_coprocessor(cs, riscv_gdb_get_vector,
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riscv_gdb_set_vector,
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ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs),
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0);
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}
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switch (mcc->misa_mxl_max) {
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case MXL_RV32:
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gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
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riscv_gdb_set_virtual,
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gdb_find_static_feature("riscv-32bit-virtual.xml"),
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0);
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break;
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case MXL_RV64:
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case MXL_RV128:
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gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
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riscv_gdb_set_virtual,
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gdb_find_static_feature("riscv-64bit-virtual.xml"),
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0);
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break;
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default:
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g_assert_not_reached();
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}
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if (cpu->cfg.ext_zicsr) {
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gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
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riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs),
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0);
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}
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}
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