qemu/include/hw/riscv
Michael Clark d78940ec5d RISC-V: Use atomic_cmpxchg to update PLIC bitmaps
The PLIC previously used a mutex to protect against concurrent
access to the claimed and pending bitfields. Instead of using
a mutex, we update the bitfields using atomic_cmpxchg.

Rename sifive_plic_num_irqs_pending to sifive_plic_irqs_pending
and add an early out if any interrupts are pending as the
count of pending interrupts is not used.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2018-09-04 13:19:31 -07:00
..
riscv_hart.h RISC-V HART Array 2018-03-07 08:30:28 +13:00
riscv_htif.h RISC-V HTIF Console 2018-03-07 08:30:28 +13:00
sifive_clint.h RISC-V: Replace hardcoded constants with enum values 2018-05-06 10:39:38 +12:00
sifive_e.h hw/riscv/sifive_e: Create a SiFive E SoC object 2018-07-05 15:24:25 -07:00
sifive_plic.h RISC-V: Use atomic_cmpxchg to update PLIC bitmaps 2018-09-04 13:19:31 -07:00
sifive_prci.h SiFive RISC-V PRCI Block 2018-03-07 08:30:28 +13:00
sifive_test.h SiFive RISC-V Test Finisher 2018-03-07 08:30:28 +13:00
sifive_u.h hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device 2018-07-05 15:24:25 -07:00
sifive_uart.h SiFive RISC-V UART Device 2018-03-07 08:30:28 +13:00
spike.h RISC-V: Make some header guards more specific 2018-05-06 10:39:38 +12:00
virt.h RISC-V: Make virt header comment title consistent 2018-05-06 10:39:38 +12:00