qemu/target
Peter Maydell a65dabf71a target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64
When a coprocessor instruction in an  AArch32 guest traps to AArch32
Hyp mode, the syndrome register (HSR) includes Rt and Rt2 fields
which are simply copies of the Rt and Rt2 fields from the trapped
instruction.  However, if the instruction is trapped from AArch32 to
an AArch64 higher exception level, the Rt and Rt2 fields in the
syndrome register (ESR_ELx) must be the AArch64 view of the register.
This makes a difference if the AArch32 guest was in a mode other than
User or System and it was using r13 or r14, or if it was in FIQ mode
and using r8-r14.

We don't know at translate time which AArch32 CPU mode we are in, so
we leave the values we generate in our prototype syndrome register
value at translate time as the raw Rt/Rt2 from the instruction, and
instead correct them to the AArch64 view when we find we need to take
an exception from AArch32 to AArch64 with one of these syndrome
values.

Fixes: https://bugs.launchpad.net/qemu/+bug/1879587
Reported-by: Julien Freche <julien@bedrocksystems.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200804193903.31240-1-peter.maydell@linaro.org
2020-08-05 17:31:51 +01:00
..
alpha accel/tcg: Relax va restrictions on 64-bit guests 2020-05-15 15:25:16 +01:00
arm target/arm: Fix Rt/Rt2 in ESR_ELx for copro traps from AArch32 to 64 2020-08-05 17:31:51 +01:00
avr target/avr/disas: Fix store instructions display order 2020-07-11 11:02:05 +02:00
cris x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
hppa target/hppa: Free some temps in do_sub 2020-07-24 14:28:33 -07:00
i386 target/i386: floatx80: avoid compound literals in static initializers 2020-07-27 09:40:16 +01:00
lm32 x86 and machine queue for 5.0 soft freeze 2020-03-19 14:22:46 +00:00
m68k target/m68k: consolidate physical translation offset into get_physical_address() 2020-07-06 21:39:57 +02:00
microblaze target/microblaze: monitor: Increase the number of registers reported 2020-05-14 16:01:02 +02:00
mips target/mips: Fix ADD.S FPU instruction 2020-07-14 21:49:33 +02:00
moxie cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
nios2 target/nios2: Use gen_io_start around wrctl instruction 2020-07-13 14:36:11 +01:00
openrisc softfloat: Name compare relation enum 2020-05-19 08:41:45 -07:00
ppc pseries: fix kvmppc_set_fwnmi() 2020-07-27 11:09:25 +10:00
riscv target/riscv/vector_helper: Fix build on 32-bit big endian hosts 2020-08-05 10:43:45 +02:00
rx target/rx/translate: Add missing fall through comment 2020-04-07 18:45:54 -07:00
s390x error: Eliminate error_propagate() with Coccinelle, part 1 2020-07-10 15:18:08 +02:00
sh4 gdbstub: Introduce gdb_get_float32() to get 32-bit float registers 2020-04-15 11:38:23 +01:00
sparc error: Eliminate error_propagate() with Coccinelle, part 1 2020-07-10 15:18:08 +02:00
tilegx cpu: Use DeviceClass reset instead of a special CPUClass reset 2020-03-17 19:48:10 -04:00
tricore target/tricore: Implement gdbstub 2020-06-01 16:55:13 +02:00
unicore32 target/unicore32: Prefer qemu_semihosting_log_out() over curses 2020-06-09 19:58:53 +02:00
xtensa target/xtensa fixes for 5.1: 2020-06-25 21:20:45 +01:00