qemu/target/tricore
Bastian Koppelmann a21993c7f9 target/tricore: Fix OPC2_32_RRPW_EXTR for width=0
if width was 0 we would run into the assertion:

qemu-system-tricore: tcg/tcg-op.c:217: tcg_gen_sari_i32: Assertion `arg2 >= 0 && arg2 < 32' failed.o

The instruction manual specifies undefined behaviour for this case. So
we bring this in line with the golden Infineon simlator 'tsim', which
simply writes 0 to the result in case of width=0.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2021-03-14 14:49:01 +01:00
..
cpu-param.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
cpu-qom.h qom: Remove module_obj_name parameter from OBJECT_DECLARE* macros 2020-09-18 14:12:32 -04:00
cpu.c cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass 2021-02-05 10:24:15 -10:00
cpu.h target/tricore: Remove unused definitions 2021-03-14 14:41:56 +01:00
csfr.def tricore: added CORE_ID 2018-03-02 11:46:31 +01:00
fpu_helper.c tricore: add QSEED instruction 2019-06-25 15:02:07 +02:00
gdbstub.c tricore tcg cpus: Fix Lesser GPL version number 2020-11-15 16:40:30 +01:00
helper.c target/tricore: Pass MMUAccessType to get_physical_address() 2021-03-14 14:41:56 +01:00
helper.h target/tricore: Implement a qemu excptions helper 2019-08-22 12:16:58 +02:00
meson.build meson: target 2020-08-21 06:30:35 -04:00
op_helper.c target/tricore: Implement a qemu excptions helper 2019-08-22 12:16:58 +02:00
translate.c target/tricore: Fix OPC2_32_RRPW_EXTR for width=0 2021-03-14 14:49:01 +01:00
tricore-defs.h tcg: Split out target/arch/cpu-param.h 2019-06-10 07:03:34 -07:00
tricore-opcodes.h Supply missing header guards 2019-06-12 13:20:21 +02:00