mirror of
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f79283fdb8
GCC13 reports an error :
../target/s390x/tcg/fpu_helper.c:123:5: error: conflicting types for ‘float_comp_to_cc’ due to enum/integer mismatch; have ‘int(CPUS390XState *, FloatRelation)’ {aka ‘int(struct CPUArchState *, FloatRelation)’} [-Werror=enum-int-mismatch]
123 | int float_comp_to_cc(CPUS390XState *env, FloatRelation float_compare)
| ^~~~~~~~~~~~~~~~
In file included from ../target/s390x/tcg/fpu_helper.c:23:
../target/s390x/s390x-internal.h:302:5: note: previous declaration of ‘float_comp_to_cc’ with type ‘int(CPUS390XState *, int)’ {aka ‘int(struct CPUArchState *, int)’}
302 | int float_comp_to_cc(CPUS390XState *env, int float_compare);
| ^~~~~~~~~~~~~~~~
Fixes: 71bfd65c5f ("softfloat: Name compare relation enum")
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230321161609.716474-3-clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
410 lines
16 KiB
C
410 lines
16 KiB
C
/*
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* s390x internal definitions and helpers
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*
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* Copyright (c) 2009 Ulrich Hecht
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef S390X_INTERNAL_H
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#define S390X_INTERNAL_H
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#include "cpu.h"
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#include "fpu/softfloat.h"
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#ifndef CONFIG_USER_ONLY
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typedef struct LowCore {
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/* prefix area: defined by architecture */
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uint32_t ccw1[2]; /* 0x000 */
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uint32_t ccw2[4]; /* 0x008 */
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uint8_t pad1[0x80 - 0x18]; /* 0x018 */
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uint32_t ext_params; /* 0x080 */
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uint16_t cpu_addr; /* 0x084 */
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uint16_t ext_int_code; /* 0x086 */
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uint16_t svc_ilen; /* 0x088 */
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uint16_t svc_code; /* 0x08a */
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uint16_t pgm_ilen; /* 0x08c */
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uint16_t pgm_code; /* 0x08e */
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uint32_t data_exc_code; /* 0x090 */
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uint16_t mon_class_num; /* 0x094 */
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uint16_t per_perc_atmid; /* 0x096 */
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uint64_t per_address; /* 0x098 */
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uint8_t exc_access_id; /* 0x0a0 */
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uint8_t per_access_id; /* 0x0a1 */
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uint8_t op_access_id; /* 0x0a2 */
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uint8_t ar_access_id; /* 0x0a3 */
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uint8_t pad2[0xA8 - 0xA4]; /* 0x0a4 */
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uint64_t trans_exc_code; /* 0x0a8 */
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uint64_t monitor_code; /* 0x0b0 */
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uint16_t subchannel_id; /* 0x0b8 */
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uint16_t subchannel_nr; /* 0x0ba */
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uint32_t io_int_parm; /* 0x0bc */
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uint32_t io_int_word; /* 0x0c0 */
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uint8_t pad3[0xc8 - 0xc4]; /* 0x0c4 */
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uint32_t stfl_fac_list; /* 0x0c8 */
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uint8_t pad4[0xe8 - 0xcc]; /* 0x0cc */
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uint64_t mcic; /* 0x0e8 */
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uint8_t pad5[0xf4 - 0xf0]; /* 0x0f0 */
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uint32_t external_damage_code; /* 0x0f4 */
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uint64_t failing_storage_address; /* 0x0f8 */
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uint8_t pad6[0x110 - 0x100]; /* 0x100 */
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uint64_t per_breaking_event_addr; /* 0x110 */
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uint8_t pad7[0x120 - 0x118]; /* 0x118 */
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PSW restart_old_psw; /* 0x120 */
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PSW external_old_psw; /* 0x130 */
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PSW svc_old_psw; /* 0x140 */
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PSW program_old_psw; /* 0x150 */
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PSW mcck_old_psw; /* 0x160 */
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PSW io_old_psw; /* 0x170 */
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uint8_t pad8[0x1a0 - 0x180]; /* 0x180 */
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PSW restart_new_psw; /* 0x1a0 */
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PSW external_new_psw; /* 0x1b0 */
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PSW svc_new_psw; /* 0x1c0 */
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PSW program_new_psw; /* 0x1d0 */
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PSW mcck_new_psw; /* 0x1e0 */
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PSW io_new_psw; /* 0x1f0 */
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uint8_t pad13[0x11b0 - 0x200]; /* 0x200 */
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uint64_t mcesad; /* 0x11B0 */
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/* 64 bit extparam used for pfault, diag 250 etc */
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uint64_t ext_params2; /* 0x11B8 */
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uint8_t pad14[0x1200 - 0x11C0]; /* 0x11C0 */
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/* System info area */
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uint64_t floating_pt_save_area[16]; /* 0x1200 */
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uint64_t gpregs_save_area[16]; /* 0x1280 */
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uint32_t st_status_fixed_logout[4]; /* 0x1300 */
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uint8_t pad15[0x1318 - 0x1310]; /* 0x1310 */
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uint32_t prefixreg_save_area; /* 0x1318 */
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uint32_t fpt_creg_save_area; /* 0x131c */
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uint8_t pad16[0x1324 - 0x1320]; /* 0x1320 */
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uint32_t tod_progreg_save_area; /* 0x1324 */
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uint64_t cpu_timer_save_area; /* 0x1328 */
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uint64_t clock_comp_save_area; /* 0x1330 */
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uint8_t pad17[0x1340 - 0x1338]; /* 0x1338 */
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uint32_t access_regs_save_area[16]; /* 0x1340 */
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uint64_t cregs_save_area[16]; /* 0x1380 */
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/* align to the top of the prefix area */
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uint8_t pad18[0x2000 - 0x1400]; /* 0x1400 */
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} QEMU_PACKED LowCore;
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QEMU_BUILD_BUG_ON(sizeof(LowCore) != 8192);
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#endif /* CONFIG_USER_ONLY */
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#define MAX_ILEN 6
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/* While the PoO talks about ILC (a number between 1-3) what is actually
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stored in LowCore is shifted left one bit (an even between 2-6). As
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this is the actual length of the insn and therefore more useful, that
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is what we want to pass around and manipulate. To make sure that we
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have applied this distinction universally, rename the "ILC" to "ILEN". */
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static inline int get_ilen(uint8_t opc)
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{
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switch (opc >> 6) {
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case 0:
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return 2;
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case 1:
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case 2:
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return 4;
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default:
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return 6;
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}
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}
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/* Compute the ATMID field that is stored in the per_perc_atmid lowcore
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entry when a PER exception is triggered. */
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static inline uint8_t get_per_atmid(CPUS390XState *env)
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{
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return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
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(1 << 6) |
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((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
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((env->psw.mask & PSW_MASK_DAT) ? (1 << 4) : 0) |
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((env->psw.mask & PSW_ASC_SECONDARY) ? (1 << 3) : 0) |
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((env->psw.mask & PSW_ASC_ACCREG) ? (1 << 2) : 0);
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}
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static inline uint64_t wrap_address(CPUS390XState *env, uint64_t a)
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{
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if (!(env->psw.mask & PSW_MASK_64)) {
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if (!(env->psw.mask & PSW_MASK_32)) {
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/* 24-Bit mode */
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a &= 0x00ffffff;
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} else {
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/* 31-Bit mode */
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a &= 0x7fffffff;
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}
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}
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return a;
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}
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/* CC optimization */
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/* Instead of computing the condition codes after each x86 instruction,
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* QEMU just stores the result (called CC_DST), the type of operation
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* (called CC_OP) and whatever operands are needed (CC_SRC and possibly
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* CC_VR). When the condition codes are needed, the condition codes can
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* be calculated using this information. Condition codes are not generated
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* if they are only needed for conditional branches.
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*/
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enum cc_op {
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CC_OP_CONST0 = 0, /* CC is 0 */
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CC_OP_CONST1, /* CC is 1 */
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CC_OP_CONST2, /* CC is 2 */
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CC_OP_CONST3, /* CC is 3 */
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CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
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CC_OP_STATIC, /* CC value is env->cc_op */
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CC_OP_NZ, /* env->cc_dst != 0 */
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CC_OP_ADDU, /* dst != 0, src = carry out (0,1) */
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CC_OP_SUBU, /* dst != 0, src = borrow out (0,-1) */
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CC_OP_LTGT_32, /* signed less/greater than (32bit) */
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CC_OP_LTGT_64, /* signed less/greater than (64bit) */
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CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
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CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
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CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
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CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
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CC_OP_ADD_64, /* overflow on add (64bit) */
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CC_OP_SUB_64, /* overflow on subtraction (64bit) */
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CC_OP_ABS_64, /* sign eval on abs (64bit) */
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CC_OP_NABS_64, /* sign eval on nabs (64bit) */
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CC_OP_MULS_64, /* overflow on signed multiply (64bit) */
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CC_OP_ADD_32, /* overflow on add (32bit) */
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CC_OP_SUB_32, /* overflow on subtraction (32bit) */
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CC_OP_ABS_32, /* sign eval on abs (64bit) */
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CC_OP_NABS_32, /* sign eval on nabs (64bit) */
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CC_OP_MULS_32, /* overflow on signed multiply (32bit) */
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CC_OP_COMP_32, /* complement */
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CC_OP_COMP_64, /* complement */
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CC_OP_TM_32, /* test under mask (32bit) */
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CC_OP_TM_64, /* test under mask (64bit) */
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CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
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CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
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CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
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CC_OP_ICM, /* insert characters under mask */
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CC_OP_SLA, /* Calculate shift left signed */
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CC_OP_FLOGR, /* find leftmost one */
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CC_OP_LCBB, /* load count to block boundary */
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CC_OP_VC, /* vector compare result */
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CC_OP_MAX
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};
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#ifndef CONFIG_USER_ONLY
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static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
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uint8_t *ar)
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{
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hwaddr addr = 0;
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uint8_t reg;
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reg = ipb >> 28;
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if (reg > 0) {
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addr = env->regs[reg];
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}
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addr += (ipb >> 16) & 0xfff;
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if (ar) {
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*ar = reg;
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}
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return addr;
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}
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/* Base/displacement are at the same locations. */
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#define decode_basedisp_rs decode_basedisp_s
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#endif /* CONFIG_USER_ONLY */
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/* arch_dump.c */
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int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
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int cpuid, DumpState *s);
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/* cc_helper.c */
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const char *cc_name(enum cc_op cc_op);
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uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
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uint64_t vr);
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/* cpu.c */
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#ifndef CONFIG_USER_ONLY
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unsigned int s390_cpu_halt(S390CPU *cpu);
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void s390_cpu_unhalt(S390CPU *cpu);
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void s390_cpu_init_sysemu(Object *obj);
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bool s390_cpu_realize_sysemu(DeviceState *dev, Error **errp);
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void s390_cpu_finalize(Object *obj);
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void s390_cpu_class_init_sysemu(CPUClass *cc);
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void s390_cpu_machine_reset_cb(void *opaque);
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#else
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static inline unsigned int s390_cpu_halt(S390CPU *cpu)
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{
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return 0;
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}
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static inline void s390_cpu_unhalt(S390CPU *cpu)
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{
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}
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#endif /* CONFIG_USER_ONLY */
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/* cpu_models.c */
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void s390_cpu_model_class_register_props(ObjectClass *oc);
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void s390_realize_cpu_model(CPUState *cs, Error **errp);
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S390CPUModel *get_max_cpu_model(Error **errp);
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void apply_cpu_model(const S390CPUModel *model, Error **errp);
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ObjectClass *s390_cpu_class_by_name(const char *name);
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/* excp_helper.c */
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void s390x_cpu_debug_excp_handler(CPUState *cs);
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void s390_cpu_do_interrupt(CPUState *cpu);
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bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
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#ifdef CONFIG_USER_ONLY
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void s390_cpu_record_sigsegv(CPUState *cs, vaddr address,
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MMUAccessType access_type,
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bool maperr, uintptr_t retaddr);
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void s390_cpu_record_sigbus(CPUState *cs, vaddr address,
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MMUAccessType access_type, uintptr_t retaddr);
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#else
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bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr);
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G_NORETURN void s390x_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t retaddr);
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#endif
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/* fpu_helper.c */
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uint32_t set_cc_nz_f32(float32 v);
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uint32_t set_cc_nz_f64(float64 v);
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uint32_t set_cc_nz_f128(float128 v);
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#define S390_IEEE_MASK_INVALID 0x80
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#define S390_IEEE_MASK_DIVBYZERO 0x40
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#define S390_IEEE_MASK_OVERFLOW 0x20
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#define S390_IEEE_MASK_UNDERFLOW 0x10
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#define S390_IEEE_MASK_INEXACT 0x08
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#define S390_IEEE_MASK_QUANTUM 0x04
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uint8_t s390_softfloat_exc_to_ieee(unsigned int exc);
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int s390_swap_bfp_rounding_mode(CPUS390XState *env, int m3);
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void s390_restore_bfp_rounding_mode(CPUS390XState *env, int old_mode);
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int float_comp_to_cc(CPUS390XState *env, FloatRelation float_compare);
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#define DCMASK_ZERO 0x0c00
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#define DCMASK_NORMAL 0x0300
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#define DCMASK_SUBNORMAL 0x00c0
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#define DCMASK_INFINITY 0x0030
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#define DCMASK_QUIET_NAN 0x000c
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#define DCMASK_SIGNALING_NAN 0x0003
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#define DCMASK_NAN 0x000f
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#define DCMASK_NEGATIVE 0x0555
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uint16_t float32_dcmask(CPUS390XState *env, float32 f1);
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uint16_t float64_dcmask(CPUS390XState *env, float64 f1);
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uint16_t float128_dcmask(CPUS390XState *env, float128 f1);
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/* gdbstub.c */
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int s390_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
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int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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void s390_cpu_gdb_init(CPUState *cs);
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/* helper.c */
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void s390_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
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void do_restart_interrupt(CPUS390XState *env);
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#ifndef CONFIG_USER_ONLY
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void s390_cpu_recompute_watchpoints(CPUState *cs);
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void s390x_tod_timer(void *opaque);
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void s390x_cpu_timer(void *opaque);
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void s390_handle_wait(S390CPU *cpu);
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hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
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hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
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#define S390_STORE_STATUS_DEF_ADDR offsetof(LowCore, floating_pt_save_area)
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int s390_store_status(S390CPU *cpu, hwaddr addr, bool store_arch);
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int s390_store_adtl_status(S390CPU *cpu, hwaddr addr, hwaddr len);
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LowCore *cpu_map_lowcore(CPUS390XState *env);
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void cpu_unmap_lowcore(LowCore *lowcore);
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#endif /* CONFIG_USER_ONLY */
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/* interrupt.c */
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void trigger_pgm_exception(CPUS390XState *env, uint32_t code);
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void cpu_inject_clock_comparator(S390CPU *cpu);
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void cpu_inject_cpu_timer(S390CPU *cpu);
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void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr);
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int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr);
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bool s390_cpu_has_io_int(S390CPU *cpu);
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bool s390_cpu_has_ext_int(S390CPU *cpu);
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bool s390_cpu_has_mcck_int(S390CPU *cpu);
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bool s390_cpu_has_int(S390CPU *cpu);
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bool s390_cpu_has_restart_int(S390CPU *cpu);
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bool s390_cpu_has_stop_int(S390CPU *cpu);
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void cpu_inject_restart(S390CPU *cpu);
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void cpu_inject_stop(S390CPU *cpu);
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/* ioinst.c */
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void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
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void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
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void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
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void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
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uintptr_t ra);
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void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
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uintptr_t ra);
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void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb, uintptr_t ra);
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void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb,
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uintptr_t ra);
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int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb, uintptr_t ra);
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void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb, uintptr_t ra);
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void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
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uint32_t ipb, uintptr_t ra);
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void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
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void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
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void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1, uintptr_t ra);
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/* mem_helper.c */
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target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr);
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void probe_write_access(CPUS390XState *env, uint64_t addr, uint64_t len,
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uintptr_t ra);
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/* mmu_helper.c */
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bool mmu_absolute_addr_valid(target_ulong addr, bool is_write);
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/* Special access mode only valid for mmu_translate() */
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#define MMU_S390_LRA -1
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int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
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target_ulong *raddr, int *flags, uint64_t *tec);
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int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
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target_ulong *addr, int *flags, uint64_t *tec);
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/* misc_helper.c */
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int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
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void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3,
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uintptr_t ra);
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/* translate.c */
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void s390x_translate_init(void);
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void s390x_restore_state_to_opc(CPUState *cs,
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const TranslationBlock *tb,
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const uint64_t *data);
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/* sigp.c */
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int handle_sigp(CPUS390XState *env, uint8_t order, uint64_t r1, uint64_t r3);
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void do_stop_interrupt(CPUS390XState *env);
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#endif /* S390X_INTERNAL_H */
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