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98281984a3
These new mmu indexes will be helpful for improving paging and code throughout the target. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221002172956.265735-6-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
33 lines
746 B
C
33 lines
746 B
C
/*
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* i386 cpu parameters for qemu.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* SPDX-License-Identifier: LGPL-2.0+
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*/
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#ifndef I386_CPU_PARAM_H
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#define I386_CPU_PARAM_H
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#ifdef TARGET_X86_64
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# define TARGET_LONG_BITS 64
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# define TARGET_PHYS_ADDR_SPACE_BITS 52
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/*
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* ??? This is really 48 bits, sign-extended, but the only thing
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* accessible to userland with bit 48 set is the VSYSCALL, and that
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* is handled via other mechanisms.
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*/
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# define TARGET_VIRT_ADDR_SPACE_BITS 47
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#else
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# define TARGET_LONG_BITS 32
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# define TARGET_PHYS_ADDR_SPACE_BITS 36
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif
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#define TARGET_PAGE_BITS 12
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#define NB_MMU_MODES 5
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#ifndef CONFIG_USER_ONLY
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# define TARGET_TB_PCREL 1
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#endif
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#endif
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