Bastian Koppelmann 5dc1fbae70 target-tricore: Fix wrong precedences on psw_write ... Wrong braces on the restore of the cached TCGv SV and V bit could lead to a wrong PSW. While at this it removes unnecessary braces for the restore of the cached TCGv AV and SAV bits. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>		2016-02-25 12:51:31 +01:00
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cpu-qom.h	target-tricore: Remove the dummy interrupt boilerplate	2014-09-25 18:54:22 +01:00
cpu.c	tricore: Clean up includes	2016-01-29 15:07:25 +00:00
cpu.h	all: Clean up includes	2016-02-23 12:43:05 +00:00
csfr.def	target-tricore: Fix new typos	2015-01-15 10:44:13 +03:00
helper.c	target-tricore: Fix wrong precedences on psw_write	2016-02-25 12:51:31 +01:00
helper.h	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00
Makefile.objs	target-tricore: Add target stubs and qom-cpu	2014-09-01 14:49:20 +01:00
op_helper.c	target-tricore: fix save_context_upper using env->PSW	2016-02-25 12:51:27 +01:00
translate.c	tcg: Change tcg_global_mem_new_* to take a TCGv_ptr	2016-02-09 10:19:32 +11:00
tricore-defs.h	target-tricore: Add target stubs and qom-cpu	2014-09-01 14:49:20 +01:00
tricore-opcodes.h	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00