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The various Intel CPU manuals claim that SGDT and SIDT can write either 24-bits or 32-bits depending upon the operand size, but this is incorrect. Not only do the Intel CPU manuals give contradictory information between processor revisions, but this information doesn't even match real-life behaviour. In fact, tests on real hardware show that the CPU always writes 32-bits for SGDT and SIDT, and this behaviour is required for at least OS/2 Warp and WFW 3.11 with Win32s to function correctly. Remove the masking applied due to the operand size for SGDT and SIDT so that the TCG behaviour matches the behaviour on real hardware. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2198 -- MCA: Whilst I don't have a copy of OS/2 Warp handy, I've confirmed that this patch fixes the issue in WFW 3.11 with Win32s. For more technical information I highly recommend the excellent write-up at https://www.os2museum.com/wp/sgdtsidt-fiction-and-reality/. Message-ID: <20240419195147.434894-1-mark.cave-ayland@ilande.co.uk> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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| .. | ||
| sysemu | ||
| user | ||
| bpt_helper.c | ||
| cc_helper.c | ||
| cc_helper_template.h.inc | ||
| decode-new.c.inc | ||
| decode-new.h | ||
| emit.c.inc | ||
| excp_helper.c | ||
| fpu_helper.c | ||
| helper-tcg.h | ||
| int_helper.c | ||
| mem_helper.c | ||
| meson.build | ||
| misc_helper.c | ||
| mpx_helper.c | ||
| ops_sse_header.h.inc | ||
| seg_helper.c | ||
| seg_helper.h | ||
| shift_helper_template.h.inc | ||
| tcg-cpu.c | ||
| tcg-cpu.h | ||
| tcg-stub.c | ||
| translate.c | ||