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5be2c12337
Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
70 lines
2.6 KiB
Plaintext
70 lines
2.6 KiB
Plaintext
# Thumb2 instructions
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#
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# Copyright (c) 2019 Linaro, Ltd
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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# This file is processed by scripts/decodetree.py
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#
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&s_rrr_shi !extern s rd rn rm shim shty
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&s_rrr_shr !extern s rn rd rm rs shty
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# Data-processing (register)
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%imm5_12_6 12:3 6:2
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@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
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&s_rrr_shi shim=%imm5_12_6
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@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
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&s_rrr_shi shim=%imm5_12_6 rn=0
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@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
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&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
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{
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TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
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AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
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}
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BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
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{
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MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
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ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
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}
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{
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MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
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ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi
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}
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{
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TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi
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EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi
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}
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# PKHBT, PKHTB at opc1 = 0110
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{
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CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi
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ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi
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}
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ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi
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SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
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{
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CMP_xrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi
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SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi
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}
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RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
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# Data-processing (register-shifted register)
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MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
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&s_rrr_shr rn=0
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