qemu/target/mips
Fredrik Noring a95c4c26f1 target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions
The three-operand MADD and MADDU are specific to R5900 cores.

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03 17:52:52 +01:00
..
cp0_timer.c
cpu-qom.h
cpu.c target/mips: Add disassembler support for nanoMIPS 2018-10-25 22:13:33 +02:00
cpu.h target/mips: Introduce MXU registers 2018-10-29 14:13:47 +01:00
dsp_helper.c
gdbstub.c
helper.c
helper.h
internal.h
kvm.c
kvm_mips.h
lmi_helper.c
machine.c vmstate: constify VMStateField 2018-11-27 15:35:15 +01:00
Makefile.objs
mips-defs.h target/mips: Define a bit for MXU in insn_flags 2018-10-29 14:13:47 +01:00
mips-semi.c
msa_helper.c
op_helper.c
TODO
trace-events
translate.c target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions 2019-01-03 17:52:52 +01:00
translate_init.inc.c target/mips: Disable R5900 support 2018-11-17 19:29:34 +01:00