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https://gitlab.com/qemu-project/qemu
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3b34ee6780
Replace some debug printf() calls by qemu_log_mask(LOG_GUEST_ERROR). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20200524164503.11944-1-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
146 lines
3.6 KiB
C
146 lines
3.6 KiB
C
/*
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* INTC device simulation in PKUnity SoC
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*
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* Copyright (C) 2010-2012 Guan Xuetao
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation, or any later version.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#undef DEBUG_PUV3
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#include "hw/unicore32/puv3.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#define TYPE_PUV3_INTC "puv3_intc"
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#define PUV3_INTC(obj) OBJECT_CHECK(PUV3INTCState, (obj), TYPE_PUV3_INTC)
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typedef struct PUV3INTCState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq parent_irq;
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uint32_t reg_ICMR;
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uint32_t reg_ICPR;
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} PUV3INTCState;
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/* Update interrupt status after enabled or pending bits have been changed. */
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static void puv3_intc_update(PUV3INTCState *s)
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{
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if (s->reg_ICMR & s->reg_ICPR) {
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qemu_irq_raise(s->parent_irq);
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} else {
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qemu_irq_lower(s->parent_irq);
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}
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}
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/* Process a change in an external INTC input. */
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static void puv3_intc_handler(void *opaque, int irq, int level)
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{
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PUV3INTCState *s = opaque;
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DPRINTF("irq 0x%x, level 0x%x\n", irq, level);
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if (level) {
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s->reg_ICPR |= (1 << irq);
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} else {
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s->reg_ICPR &= ~(1 << irq);
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}
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puv3_intc_update(s);
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}
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static uint64_t puv3_intc_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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PUV3INTCState *s = opaque;
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uint32_t ret = 0;
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switch (offset) {
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case 0x04: /* INTC_ICMR */
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ret = s->reg_ICMR;
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break;
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case 0x0c: /* INTC_ICIP */
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ret = s->reg_ICPR; /* the same value with ICPR */
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad read offset 0x%"HWADDR_PRIx"\n",
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__func__, offset);
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}
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DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
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return ret;
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}
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static void puv3_intc_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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PUV3INTCState *s = opaque;
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DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
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switch (offset) {
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case 0x00: /* INTC_ICLR */
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case 0x14: /* INTC_ICCR */
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break;
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case 0x04: /* INTC_ICMR */
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s->reg_ICMR = value;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad write offset 0x%"HWADDR_PRIx"\n",
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__func__, offset);
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return;
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}
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puv3_intc_update(s);
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}
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static const MemoryRegionOps puv3_intc_ops = {
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.read = puv3_intc_read,
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.write = puv3_intc_write,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void puv3_intc_realize(DeviceState *dev, Error **errp)
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{
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PUV3INTCState *s = PUV3_INTC(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR);
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sysbus_init_irq(sbd, &s->parent_irq);
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s->reg_ICMR = 0;
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s->reg_ICPR = 0;
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memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc",
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PUV3_REGS_OFFSET);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void puv3_intc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = puv3_intc_realize;
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}
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static const TypeInfo puv3_intc_info = {
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.name = TYPE_PUV3_INTC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(PUV3INTCState),
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.class_init = puv3_intc_class_init,
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};
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static void puv3_intc_register_type(void)
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{
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type_register_static(&puv3_intc_info);
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}
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type_init(puv3_intc_register_type)
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