qemu/target
Peter Maydell 4f9a4cd37e 1)
Performance improvement
 Add pkt and insn to DisasContext
 Many functions need information from all 3 structures, so merge
 them together.
 
 2)
 Bug fix
 Fix predicated assignment to .tmp and .cur
 
 3)
 Performance improvement
 Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat
 These functions will not be handled by idef-parser
 
 4-11)
 The final 8 patches improve change-of-flow handling.
 
 Currently, we set the PC to a new address before exiting a TB.  The
 ultimate goal is to use direct block chaining.  However, several steps
 are needed along the way.
 
 4)
 When a packet has more than one change-of-flow (COF) instruction, only
 the first one taken is considered.  The runtime bookkeeping is only
 needed when there is more than one COF instruction in a packet.
 
 5, 6)
 Remove PC and next_PC from the runtime state and always use a
 translation-time constant.  Note that next_PC is used by call instructions
 to set LR and by conditional COF instructions to set the fall-through
 address.
 
 7, 8, 9)
 Add helper overrides for COF instructions.  In particular, we must
 distinguish those that use a PC-relative address for the destination.
 These are candidates for direct block chaining later.
 
 10)
 Use direct block chaining for packets that have a single PC-relative
 COF instruction.  Instead of generating the code while processing the
 instruction, we record the effect in DisasContext and generate the code
 during gen_end_tb.
 
 11)
 Use direct block chaining for tight loops.  We look for TBs that end
 with an endloop0 that will branch back to the TB start address.
 
 12-21)
 Instruction definition parser (idef-parser) from rev.ng
 Parses the instruction semantics and generates TCG
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Merge tag 'pull-hex-20221216-1' of https://github.com/quic/qemu into staging

1)
Performance improvement
Add pkt and insn to DisasContext
Many functions need information from all 3 structures, so merge
them together.

2)
Bug fix
Fix predicated assignment to .tmp and .cur

3)
Performance improvement
Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat
These functions will not be handled by idef-parser

4-11)
The final 8 patches improve change-of-flow handling.

Currently, we set the PC to a new address before exiting a TB.  The
ultimate goal is to use direct block chaining.  However, several steps
are needed along the way.

4)
When a packet has more than one change-of-flow (COF) instruction, only
the first one taken is considered.  The runtime bookkeeping is only
needed when there is more than one COF instruction in a packet.

5, 6)
Remove PC and next_PC from the runtime state and always use a
translation-time constant.  Note that next_PC is used by call instructions
to set LR and by conditional COF instructions to set the fall-through
address.

7, 8, 9)
Add helper overrides for COF instructions.  In particular, we must
distinguish those that use a PC-relative address for the destination.
These are candidates for direct block chaining later.

10)
Use direct block chaining for packets that have a single PC-relative
COF instruction.  Instead of generating the code while processing the
instruction, we record the effect in DisasContext and generate the code
during gen_end_tb.

11)
Use direct block chaining for tight loops.  We look for TBs that end
with an endloop0 that will branch back to the TB start address.

12-21)
Instruction definition parser (idef-parser) from rev.ng
Parses the instruction semantics and generates TCG

# gpg: Signature made Fri 16 Dec 2022 20:41:53 GMT
# gpg:                using RSA key 3635C788CE62B91FD4C59AB47B0244FB12DE4422
# gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 3635 C788 CE62 B91F D4C5  9AB4 7B02 44FB 12DE 4422

* tag 'pull-hex-20221216-1' of https://github.com/quic/qemu: (21 commits)
  target/hexagon: import additional tests
  target/hexagon: call idef-parser functions
  target/hexagon: import parser for idef-parser
  target/hexagon: import lexer for idef-parser
  target/hexagon: prepare input for the idef-parser
  target/hexagon: introduce new helper functions
  target/hexagon: make helper functions non-static
  target/hexagon: make slot number an unsigned
  target/hexagon: import README for idef-parser
  target/hexagon: update MAINTAINERS for idef-parser
  Hexagon (target/hexagon) Use direct block chaining for tight loops
  Hexagon (target/hexagon) Use direct block chaining for direct jump/branch
  Hexagon (target/hexagon) Add overrides for various forms of jump
  Hexagon (target/hexagon) Add overrides for compound compare and jump
  Hexagon (target/hexagon) Add overrides for direct call instructions
  Hexagon (target/hexagon) Remove next_PC from runtime state
  Hexagon (target/hexagon) Remove PC from the runtime state
  Hexagon (target/hexagon) Only use branch_taken when packet has multi cof
  Hexagon (target/hexagon) Add overrides for S2_asr_r_r_sat/S2_asl_r_r_sat
  Hexagon (target/hexagon) Fix predicated assignment to .tmp and .cur
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-12-18 17:02:11 +00:00
..
alpha accel/tcg: Remove will_exit argument from cpu_restore_state 2022-11-01 08:31:41 +11:00
arm target/arm: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
avr target/avr: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
cris target/cris: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
hexagon 1) 2022-12-18 17:02:11 +00:00
hppa target/hppa: Convert to tcg_ops restore_state_to_opc 2022-10-26 11:11:28 +10:00
i386 target/i386: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
loongarch target/loongarch: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
m68k target/m68k: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
microblaze target/microblaze: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
mips target/mips: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
nios2 target/nios2: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
openrisc target/openrisc: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
ppc target/ppc: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
riscv target/riscv: Convert to 3-phase reset 2022-12-16 15:58:15 +00:00
rx target/rx: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
s390x target/s390x: The MVCP and MVCS instructions are not privileged 2022-12-15 15:02:34 +01:00
sh4 target/sh4: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
sparc target/sparc: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
tricore target/tricore: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
xtensa target/xtensa: Convert to 3-phase reset 2022-12-16 15:58:16 +00:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00