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https://gitlab.com/qemu-project/qemu
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5dc5d9f055
Commit 36388314fe moved most of the
interrupt logic to cpu-exec.c. Remove the remaining useless code
and fix software interrupts.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Acked-by: Edgar E. Iglesias <edgar@axis.com>
Tested-by: Edgar E. Iglesias <edgar@axis.com>
65 lines
1.9 KiB
C
65 lines
1.9 KiB
C
/*
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* QEMU MIPS interrupt support
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "mips_cpudevs.h"
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#include "cpu.h"
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static void cpu_mips_irq_request(void *opaque, int irq, int level)
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{
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CPUState *env = (CPUState *)opaque;
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if (irq < 0 || irq > 7)
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return;
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if (level) {
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env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
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} else {
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env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
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}
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if (env->CP0_Cause & CP0Ca_IP_mask) {
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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void cpu_mips_irq_init_cpu(CPUState *env)
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{
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qemu_irq *qi;
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int i;
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qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8);
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for (i = 0; i < 8; i++) {
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env->irq[i] = qi[i];
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}
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}
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void cpu_mips_soft_irq(CPUState *env, int irq, int level)
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{
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if (irq < 0 || irq > 2) {
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return;
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}
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qemu_set_irq(env->irq[irq], level);
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}
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