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7212812263
Always reserve r3 for tlb softmmu lookup. Fix a bug in user-only ALL_QLDST_REGS, in that r14 is clobbered by the BLNE that leads to the misaligned trap. Remove r0+r1 from user-only ALL_QLDST_REGS; I believe these had been reserved for bswap, which we no longer perform during qemu_st. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
47 lines
982 B
C
47 lines
982 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define Arm target-specific constraint sets.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* C_On_Im(...) defines a constraint set with <n> outputs and <m> inputs.
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* Each operand should be a sequence of constraint letters as defined by
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* tcg-target-con-str.h; the constraint combination is inclusive or.
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*/
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C_O0_I1(r)
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C_O0_I2(r, r)
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C_O0_I2(r, rIN)
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C_O0_I2(q, q)
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C_O0_I2(w, r)
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C_O0_I3(q, q, q)
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C_O0_I3(Q, p, q)
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C_O0_I4(r, r, rI, rI)
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C_O0_I4(Q, p, q, q)
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C_O1_I1(r, q)
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C_O1_I1(r, r)
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C_O1_I1(w, r)
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C_O1_I1(w, w)
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C_O1_I1(w, wr)
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C_O1_I2(r, 0, rZ)
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C_O1_I2(r, q, q)
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C_O1_I2(r, r, r)
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C_O1_I2(r, r, rI)
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C_O1_I2(r, r, rIK)
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C_O1_I2(r, r, rIN)
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C_O1_I2(r, r, ri)
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C_O1_I2(r, rZ, rZ)
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C_O1_I2(w, 0, w)
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C_O1_I2(w, w, w)
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C_O1_I2(w, w, wO)
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C_O1_I2(w, w, wV)
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C_O1_I2(w, w, wZ)
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C_O1_I3(w, w, w, w)
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C_O1_I4(r, r, r, rI, rI)
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C_O1_I4(r, r, rIN, rIK, 0)
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C_O2_I1(e, p, q)
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C_O2_I2(e, p, q, q)
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C_O2_I2(r, r, r, r)
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C_O2_I4(r, r, r, r, rIN, rIK)
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C_O2_I4(r, r, rI, rI, rIN, rIK)
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