mirror of
https://gitlab.com/qemu-project/qemu
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566 lines
16 KiB
C
566 lines
16 KiB
C
/*
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* ARM Integrator CP System emulation.
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*
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* Copyright (c) 2005-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL
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*/
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#include "hw/sysbus.h"
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#include "hw/devices.h"
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#include "hw/boards.h"
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#include "hw/arm-misc.h"
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#include "net/net.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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typedef struct {
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t memsz;
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MemoryRegion flash;
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uint32_t cm_osc;
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uint32_t cm_ctrl;
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uint32_t cm_lock;
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uint32_t cm_auxosc;
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uint32_t cm_sdram;
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uint32_t cm_init;
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uint32_t cm_flags;
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uint32_t cm_nvflags;
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uint32_t int_level;
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uint32_t irq_enabled;
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uint32_t fiq_enabled;
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} integratorcm_state;
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static uint8_t integrator_spd[128] = {
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128, 8, 4, 11, 9, 1, 64, 0, 2, 0xa0, 0xa0, 0, 0, 8, 0, 1,
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0xe, 4, 0x1c, 1, 2, 0x20, 0xc0, 0, 0, 0, 0, 0x30, 0x28, 0x30, 0x28, 0x40
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};
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static uint64_t integratorcm_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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integratorcm_state *s = (integratorcm_state *)opaque;
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if (offset >= 0x100 && offset < 0x200) {
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/* CM_SPD */
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if (offset >= 0x180)
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return 0;
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return integrator_spd[offset >> 2];
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}
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switch (offset >> 2) {
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case 0: /* CM_ID */
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return 0x411a3001;
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case 1: /* CM_PROC */
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return 0;
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case 2: /* CM_OSC */
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return s->cm_osc;
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case 3: /* CM_CTRL */
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return s->cm_ctrl;
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case 4: /* CM_STAT */
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return 0x00100000;
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case 5: /* CM_LOCK */
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if (s->cm_lock == 0xa05f) {
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return 0x1a05f;
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} else {
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return s->cm_lock;
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}
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case 6: /* CM_LMBUSCNT */
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/* ??? High frequency timer. */
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hw_error("integratorcm_read: CM_LMBUSCNT");
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case 7: /* CM_AUXOSC */
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return s->cm_auxosc;
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case 8: /* CM_SDRAM */
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return s->cm_sdram;
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case 9: /* CM_INIT */
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return s->cm_init;
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case 10: /* CM_REFCT */
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/* ??? High frequency timer. */
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hw_error("integratorcm_read: CM_REFCT");
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case 12: /* CM_FLAGS */
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return s->cm_flags;
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case 14: /* CM_NVFLAGS */
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return s->cm_nvflags;
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case 16: /* CM_IRQ_STAT */
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return s->int_level & s->irq_enabled;
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case 17: /* CM_IRQ_RSTAT */
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return s->int_level;
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case 18: /* CM_IRQ_ENSET */
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return s->irq_enabled;
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case 20: /* CM_SOFT_INTSET */
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return s->int_level & 1;
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case 24: /* CM_FIQ_STAT */
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return s->int_level & s->fiq_enabled;
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case 25: /* CM_FIQ_RSTAT */
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return s->int_level;
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case 26: /* CM_FIQ_ENSET */
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return s->fiq_enabled;
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case 32: /* CM_VOLTAGE_CTL0 */
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case 33: /* CM_VOLTAGE_CTL1 */
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case 34: /* CM_VOLTAGE_CTL2 */
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case 35: /* CM_VOLTAGE_CTL3 */
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/* ??? Voltage control unimplemented. */
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return 0;
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default:
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hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
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(int)offset);
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return 0;
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}
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}
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static void integratorcm_do_remap(integratorcm_state *s)
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{
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/* Sync memory region state with CM_CTRL REMAP bit:
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* bit 0 => flash at address 0; bit 1 => RAM
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*/
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memory_region_set_enabled(&s->flash, !(s->cm_ctrl & 4));
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}
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static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
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{
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if (value & 8) {
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qemu_system_reset_request();
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}
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if ((s->cm_ctrl ^ value) & 1) {
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/* (value & 1) != 0 means the green "MISC LED" is lit.
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* We don't have any nice place to display LEDs. printf is a bad
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* idea because Linux uses the LED as a heartbeat and the output
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* will swamp anything else on the terminal.
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*/
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}
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/* Note that the RESET bit [3] always reads as zero */
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s->cm_ctrl = (s->cm_ctrl & ~5) | (value & 5);
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integratorcm_do_remap(s);
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}
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static void integratorcm_update(integratorcm_state *s)
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{
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/* ??? The CPU irq/fiq is raised when either the core module or base PIC
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are active. */
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if (s->int_level & (s->irq_enabled | s->fiq_enabled))
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hw_error("Core module interrupt\n");
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}
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static void integratorcm_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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integratorcm_state *s = (integratorcm_state *)opaque;
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switch (offset >> 2) {
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case 2: /* CM_OSC */
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if (s->cm_lock == 0xa05f)
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s->cm_osc = value;
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break;
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case 3: /* CM_CTRL */
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integratorcm_set_ctrl(s, value);
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break;
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case 5: /* CM_LOCK */
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s->cm_lock = value & 0xffff;
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break;
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case 7: /* CM_AUXOSC */
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if (s->cm_lock == 0xa05f)
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s->cm_auxosc = value;
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break;
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case 8: /* CM_SDRAM */
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s->cm_sdram = value;
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break;
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case 9: /* CM_INIT */
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/* ??? This can change the memory bus frequency. */
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s->cm_init = value;
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break;
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case 12: /* CM_FLAGSS */
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s->cm_flags |= value;
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break;
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case 13: /* CM_FLAGSC */
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s->cm_flags &= ~value;
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break;
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case 14: /* CM_NVFLAGSS */
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s->cm_nvflags |= value;
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break;
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case 15: /* CM_NVFLAGSS */
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s->cm_nvflags &= ~value;
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break;
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case 18: /* CM_IRQ_ENSET */
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s->irq_enabled |= value;
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integratorcm_update(s);
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break;
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case 19: /* CM_IRQ_ENCLR */
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s->irq_enabled &= ~value;
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integratorcm_update(s);
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break;
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case 20: /* CM_SOFT_INTSET */
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s->int_level |= (value & 1);
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integratorcm_update(s);
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break;
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case 21: /* CM_SOFT_INTCLR */
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s->int_level &= ~(value & 1);
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integratorcm_update(s);
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break;
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case 26: /* CM_FIQ_ENSET */
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s->fiq_enabled |= value;
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integratorcm_update(s);
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break;
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case 27: /* CM_FIQ_ENCLR */
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s->fiq_enabled &= ~value;
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integratorcm_update(s);
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break;
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case 32: /* CM_VOLTAGE_CTL0 */
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case 33: /* CM_VOLTAGE_CTL1 */
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case 34: /* CM_VOLTAGE_CTL2 */
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case 35: /* CM_VOLTAGE_CTL3 */
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/* ??? Voltage control unimplemented. */
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break;
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default:
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hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
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(int)offset);
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break;
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}
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}
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/* Integrator/CM control registers. */
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static const MemoryRegionOps integratorcm_ops = {
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.read = integratorcm_read,
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.write = integratorcm_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int integratorcm_init(SysBusDevice *dev)
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{
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integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
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s->cm_osc = 0x01000048;
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/* ??? What should the high bits of this value be? */
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s->cm_auxosc = 0x0007feff;
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s->cm_sdram = 0x00011122;
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if (s->memsz >= 256) {
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integrator_spd[31] = 64;
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s->cm_sdram |= 0x10;
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} else if (s->memsz >= 128) {
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integrator_spd[31] = 32;
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s->cm_sdram |= 0x0c;
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} else if (s->memsz >= 64) {
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integrator_spd[31] = 16;
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s->cm_sdram |= 0x08;
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} else if (s->memsz >= 32) {
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integrator_spd[31] = 4;
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s->cm_sdram |= 0x04;
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} else {
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integrator_spd[31] = 2;
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}
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memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
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s->cm_init = 0x00000112;
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memory_region_init_ram(&s->flash, "integrator.flash", 0x100000);
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vmstate_register_ram_global(&s->flash);
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memory_region_init_io(&s->iomem, &integratorcm_ops, s,
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"integratorcm", 0x00800000);
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sysbus_init_mmio(dev, &s->iomem);
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integratorcm_do_remap(s);
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/* ??? Save/restore. */
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return 0;
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}
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/* Integrator/CP hardware emulation. */
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/* Primary interrupt controller. */
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typedef struct icp_pic_state
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{
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SysBusDevice busdev;
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MemoryRegion iomem;
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uint32_t level;
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uint32_t irq_enabled;
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uint32_t fiq_enabled;
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qemu_irq parent_irq;
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qemu_irq parent_fiq;
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} icp_pic_state;
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static void icp_pic_update(icp_pic_state *s)
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{
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uint32_t flags;
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flags = (s->level & s->irq_enabled);
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qemu_set_irq(s->parent_irq, flags != 0);
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flags = (s->level & s->fiq_enabled);
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qemu_set_irq(s->parent_fiq, flags != 0);
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}
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static void icp_pic_set_irq(void *opaque, int irq, int level)
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{
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icp_pic_state *s = (icp_pic_state *)opaque;
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if (level)
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s->level |= 1 << irq;
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else
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s->level &= ~(1 << irq);
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icp_pic_update(s);
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}
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static uint64_t icp_pic_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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icp_pic_state *s = (icp_pic_state *)opaque;
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switch (offset >> 2) {
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case 0: /* IRQ_STATUS */
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return s->level & s->irq_enabled;
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case 1: /* IRQ_RAWSTAT */
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return s->level;
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case 2: /* IRQ_ENABLESET */
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return s->irq_enabled;
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case 4: /* INT_SOFTSET */
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return s->level & 1;
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case 8: /* FRQ_STATUS */
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return s->level & s->fiq_enabled;
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case 9: /* FRQ_RAWSTAT */
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return s->level;
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case 10: /* FRQ_ENABLESET */
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return s->fiq_enabled;
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case 3: /* IRQ_ENABLECLR */
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case 5: /* INT_SOFTCLR */
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case 11: /* FRQ_ENABLECLR */
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default:
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printf ("icp_pic_read: Bad register offset 0x%x\n", (int)offset);
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return 0;
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}
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}
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static void icp_pic_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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icp_pic_state *s = (icp_pic_state *)opaque;
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switch (offset >> 2) {
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case 2: /* IRQ_ENABLESET */
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s->irq_enabled |= value;
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break;
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case 3: /* IRQ_ENABLECLR */
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s->irq_enabled &= ~value;
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break;
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case 4: /* INT_SOFTSET */
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if (value & 1)
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icp_pic_set_irq(s, 0, 1);
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break;
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case 5: /* INT_SOFTCLR */
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if (value & 1)
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icp_pic_set_irq(s, 0, 0);
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break;
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case 10: /* FRQ_ENABLESET */
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s->fiq_enabled |= value;
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break;
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case 11: /* FRQ_ENABLECLR */
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s->fiq_enabled &= ~value;
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break;
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case 0: /* IRQ_STATUS */
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case 1: /* IRQ_RAWSTAT */
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case 8: /* FRQ_STATUS */
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case 9: /* FRQ_RAWSTAT */
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default:
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printf ("icp_pic_write: Bad register offset 0x%x\n", (int)offset);
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return;
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}
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icp_pic_update(s);
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}
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static const MemoryRegionOps icp_pic_ops = {
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.read = icp_pic_read,
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.write = icp_pic_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static int icp_pic_init(SysBusDevice *dev)
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{
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icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
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qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
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sysbus_init_irq(dev, &s->parent_irq);
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sysbus_init_irq(dev, &s->parent_fiq);
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memory_region_init_io(&s->iomem, &icp_pic_ops, s, "icp-pic", 0x00800000);
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sysbus_init_mmio(dev, &s->iomem);
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return 0;
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}
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/* CP control registers. */
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static uint64_t icp_control_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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switch (offset >> 2) {
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case 0: /* CP_IDFIELD */
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return 0x41034003;
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case 1: /* CP_FLASHPROG */
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return 0;
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case 2: /* CP_INTREG */
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return 0;
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case 3: /* CP_DECODE */
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return 0x11;
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default:
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hw_error("icp_control_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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}
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static void icp_control_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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switch (offset >> 2) {
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case 1: /* CP_FLASHPROG */
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case 2: /* CP_INTREG */
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case 3: /* CP_DECODE */
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/* Nothing interesting implemented yet. */
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break;
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default:
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hw_error("icp_control_write: Bad offset %x\n", (int)offset);
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}
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}
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static const MemoryRegionOps icp_control_ops = {
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.read = icp_control_read,
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.write = icp_control_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void icp_control_init(hwaddr base)
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{
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MemoryRegion *io;
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io = (MemoryRegion *)g_malloc0(sizeof(MemoryRegion));
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memory_region_init_io(io, &icp_control_ops, NULL,
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"control", 0x00800000);
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memory_region_add_subregion(get_system_memory(), base, io);
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/* ??? Save/restore. */
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}
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/* Board init. */
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static struct arm_boot_info integrator_binfo = {
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.loader_start = 0x0,
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.board_id = 0x113,
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};
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static void integratorcp_init(QEMUMachineInitArgs *args)
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{
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ram_addr_t ram_size = args->ram_size;
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const char *cpu_model = args->cpu_model;
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const char *kernel_filename = args->kernel_filename;
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const char *kernel_cmdline = args->kernel_cmdline;
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const char *initrd_filename = args->initrd_filename;
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ARMCPU *cpu;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ram = g_new(MemoryRegion, 1);
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MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
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qemu_irq pic[32];
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qemu_irq *cpu_pic;
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DeviceState *dev;
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int i;
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if (!cpu_model) {
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cpu_model = "arm926";
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}
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cpu = cpu_arm_init(cpu_model);
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if (!cpu) {
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fprintf(stderr, "Unable to find CPU definition\n");
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exit(1);
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}
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memory_region_init_ram(ram, "integrator.ram", ram_size);
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vmstate_register_ram_global(ram);
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/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
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/* ??? RAM should repeat to fill physical memory space. */
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/* SDRAM at address zero*/
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memory_region_add_subregion(address_space_mem, 0, ram);
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/* And again at address 0x80000000 */
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memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
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memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
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dev = qdev_create(NULL, "integrator_core");
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qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
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qdev_init_nofail(dev);
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sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
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cpu_pic = arm_pic_init_cpu(cpu);
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dev = sysbus_create_varargs("integrator_pic", 0x14000000,
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cpu_pic[ARM_PIC_CPU_IRQ],
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cpu_pic[ARM_PIC_CPU_FIQ], NULL);
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for (i = 0; i < 32; i++) {
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pic[i] = qdev_get_gpio_in(dev, i);
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}
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sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
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sysbus_create_varargs("integrator_pit", 0x13000000,
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pic[5], pic[6], pic[7], NULL);
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sysbus_create_simple("pl031", 0x15000000, pic[8]);
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sysbus_create_simple("pl011", 0x16000000, pic[1]);
|
|
sysbus_create_simple("pl011", 0x17000000, pic[2]);
|
|
icp_control_init(0xcb000000);
|
|
sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
|
|
sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
|
|
sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
|
|
if (nd_table[0].used)
|
|
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
|
|
|
|
sysbus_create_simple("pl110", 0xc0000000, pic[22]);
|
|
|
|
integrator_binfo.ram_size = ram_size;
|
|
integrator_binfo.kernel_filename = kernel_filename;
|
|
integrator_binfo.kernel_cmdline = kernel_cmdline;
|
|
integrator_binfo.initrd_filename = initrd_filename;
|
|
arm_load_kernel(cpu, &integrator_binfo);
|
|
}
|
|
|
|
static QEMUMachine integratorcp_machine = {
|
|
.name = "integratorcp",
|
|
.desc = "ARM Integrator/CP (ARM926EJ-S)",
|
|
.init = integratorcp_init,
|
|
.is_default = 1,
|
|
DEFAULT_MACHINE_OPTIONS,
|
|
};
|
|
|
|
static void integratorcp_machine_init(void)
|
|
{
|
|
qemu_register_machine(&integratorcp_machine);
|
|
}
|
|
|
|
machine_init(integratorcp_machine_init);
|
|
|
|
static Property core_properties[] = {
|
|
DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void core_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
k->init = integratorcm_init;
|
|
dc->props = core_properties;
|
|
}
|
|
|
|
static const TypeInfo core_info = {
|
|
.name = "integrator_core",
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(integratorcm_state),
|
|
.class_init = core_class_init,
|
|
};
|
|
|
|
static void icp_pic_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
|
|
|
|
sdc->init = icp_pic_init;
|
|
}
|
|
|
|
static const TypeInfo icp_pic_info = {
|
|
.name = "integrator_pic",
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(icp_pic_state),
|
|
.class_init = icp_pic_class_init,
|
|
};
|
|
|
|
static void integratorcp_register_types(void)
|
|
{
|
|
type_register_static(&icp_pic_info);
|
|
type_register_static(&core_info);
|
|
}
|
|
|
|
type_init(integratorcp_register_types)
|