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![Peter Maydell](/assets/img/avatar_default.png)
The traditional ptimer behaviour includes a collection of weird edge case behaviours. In 2016 we improved the ptimer implementation to fix these and generally make the behaviour more flexible, with ptimers opting in to the new behaviour by passing an appropriate set of policy flags to ptimer_init(). For backwards-compatibility, we defined PTIMER_POLICY_DEFAULT (which sets no flags) to give the old weird behaviour. This turns out to be a poor choice of name, because people writing new devices which use ptimers are misled into thinking that the default is probably a sensible choice of flags, when in fact it is almost always not what you want. Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY and beef up the comment to more clearly say that new devices should not be using it. The code-change part of this commit was produced by sed -i -e 's/PTIMER_POLICY_DEFAULT/PTIMER_POLICY_LEGACY/g' $(git grep -l PTIMER_POLICY_DEFAULT) with the exception of a test name string change in tests/unit/ptimer-test.c which was added manually. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220516103058.162280-1-peter.maydell@linaro.org
420 lines
11 KiB
C
420 lines
11 KiB
C
/*
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* ARM PrimeCell Timer modules.
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*
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* Copyright (c) 2005-2006 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qemu/timer.h"
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#include "hw/irq.h"
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#include "hw/ptimer.h"
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#include "hw/qdev-properties.h"
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#include "qemu/module.h"
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#include "qemu/log.h"
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#include "qom/object.h"
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/* Common timer implementation. */
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#define TIMER_CTRL_ONESHOT (1 << 0)
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#define TIMER_CTRL_32BIT (1 << 1)
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#define TIMER_CTRL_DIV1 (0 << 2)
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#define TIMER_CTRL_DIV16 (1 << 2)
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#define TIMER_CTRL_DIV256 (2 << 2)
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#define TIMER_CTRL_IE (1 << 5)
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#define TIMER_CTRL_PERIODIC (1 << 6)
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#define TIMER_CTRL_ENABLE (1 << 7)
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typedef struct {
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ptimer_state *timer;
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uint32_t control;
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uint32_t limit;
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int freq;
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int int_level;
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qemu_irq irq;
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} arm_timer_state;
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/* Check all active timers, and schedule the next timer interrupt. */
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static void arm_timer_update(arm_timer_state *s)
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{
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/* Update interrupts. */
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if (s->int_level && (s->control & TIMER_CTRL_IE)) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static uint32_t arm_timer_read(void *opaque, hwaddr offset)
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{
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arm_timer_state *s = (arm_timer_state *)opaque;
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switch (offset >> 2) {
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case 0: /* TimerLoad */
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case 6: /* TimerBGLoad */
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return s->limit;
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case 1: /* TimerValue */
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return ptimer_get_count(s->timer);
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case 2: /* TimerControl */
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return s->control;
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case 4: /* TimerRIS */
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return s->int_level;
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case 5: /* TimerMIS */
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if ((s->control & TIMER_CTRL_IE) == 0)
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return 0;
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return s->int_level;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset %x\n", __func__, (int)offset);
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return 0;
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}
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}
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/*
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* Reset the timer limit after settings have changed.
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* May only be called from inside a ptimer transaction block.
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*/
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static void arm_timer_recalibrate(arm_timer_state *s, int reload)
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{
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uint32_t limit;
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if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
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/* Free running. */
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if (s->control & TIMER_CTRL_32BIT)
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limit = 0xffffffff;
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else
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limit = 0xffff;
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} else {
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/* Periodic. */
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limit = s->limit;
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}
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ptimer_set_limit(s->timer, limit, reload);
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}
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static void arm_timer_write(void *opaque, hwaddr offset,
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uint32_t value)
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{
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arm_timer_state *s = (arm_timer_state *)opaque;
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int freq;
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switch (offset >> 2) {
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case 0: /* TimerLoad */
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s->limit = value;
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ptimer_transaction_begin(s->timer);
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arm_timer_recalibrate(s, 1);
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ptimer_transaction_commit(s->timer);
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break;
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case 1: /* TimerValue */
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/* ??? Linux seems to want to write to this readonly register.
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Ignore it. */
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break;
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case 2: /* TimerControl */
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ptimer_transaction_begin(s->timer);
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if (s->control & TIMER_CTRL_ENABLE) {
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/* Pause the timer if it is running. This may cause some
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inaccuracy dure to rounding, but avoids a whole lot of other
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messyness. */
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ptimer_stop(s->timer);
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}
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s->control = value;
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freq = s->freq;
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/* ??? Need to recalculate expiry time after changing divisor. */
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switch ((value >> 2) & 3) {
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case 1: freq >>= 4; break;
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case 2: freq >>= 8; break;
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}
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arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
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ptimer_set_freq(s->timer, freq);
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if (s->control & TIMER_CTRL_ENABLE) {
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/* Restart the timer if still enabled. */
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ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
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}
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ptimer_transaction_commit(s->timer);
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break;
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case 3: /* TimerIntClr */
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s->int_level = 0;
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break;
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case 6: /* TimerBGLoad */
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s->limit = value;
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ptimer_transaction_begin(s->timer);
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arm_timer_recalibrate(s, 0);
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ptimer_transaction_commit(s->timer);
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset %x\n", __func__, (int)offset);
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}
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arm_timer_update(s);
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}
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static void arm_timer_tick(void *opaque)
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{
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arm_timer_state *s = (arm_timer_state *)opaque;
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s->int_level = 1;
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arm_timer_update(s);
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}
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static const VMStateDescription vmstate_arm_timer = {
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.name = "arm_timer",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(control, arm_timer_state),
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VMSTATE_UINT32(limit, arm_timer_state),
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VMSTATE_INT32(int_level, arm_timer_state),
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VMSTATE_PTIMER(timer, arm_timer_state),
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VMSTATE_END_OF_LIST()
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}
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};
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static arm_timer_state *arm_timer_init(uint32_t freq)
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{
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arm_timer_state *s;
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s = g_new0(arm_timer_state, 1);
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s->freq = freq;
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s->control = TIMER_CTRL_IE;
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s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY);
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vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s);
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return s;
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}
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/*
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* ARM PrimeCell SP804 dual timer module.
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* Docs at
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* https://developer.arm.com/documentation/ddi0271/latest/
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*/
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#define TYPE_SP804 "sp804"
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OBJECT_DECLARE_SIMPLE_TYPE(SP804State, SP804)
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struct SP804State {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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arm_timer_state *timer[2];
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uint32_t freq0, freq1;
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int level[2];
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qemu_irq irq;
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};
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static const uint8_t sp804_ids[] = {
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/* Timer ID */
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0x04, 0x18, 0x14, 0,
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/* PrimeCell ID */
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0xd, 0xf0, 0x05, 0xb1
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};
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/* Merge the IRQs from the two component devices. */
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static void sp804_set_irq(void *opaque, int irq, int level)
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{
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SP804State *s = (SP804State *)opaque;
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s->level[irq] = level;
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qemu_set_irq(s->irq, s->level[0] || s->level[1]);
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}
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static uint64_t sp804_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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SP804State *s = (SP804State *)opaque;
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if (offset < 0x20) {
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return arm_timer_read(s->timer[0], offset);
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}
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if (offset < 0x40) {
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return arm_timer_read(s->timer[1], offset - 0x20);
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}
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/* TimerPeriphID */
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if (offset >= 0xfe0 && offset <= 0xffc) {
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return sp804_ids[(offset - 0xfe0) >> 2];
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}
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switch (offset) {
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/* Integration Test control registers, which we won't support */
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case 0xf00: /* TimerITCR */
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case 0xf04: /* TimerITOP (strictly write only but..) */
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qemu_log_mask(LOG_UNIMP,
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"%s: integration test registers unimplemented\n",
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__func__);
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return 0;
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}
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset %x\n", __func__, (int)offset);
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return 0;
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}
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static void sp804_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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SP804State *s = (SP804State *)opaque;
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if (offset < 0x20) {
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arm_timer_write(s->timer[0], offset, value);
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return;
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}
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if (offset < 0x40) {
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arm_timer_write(s->timer[1], offset - 0x20, value);
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return;
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}
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/* Technically we could be writing to the Test Registers, but not likely */
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n",
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__func__, (int)offset);
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}
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static const MemoryRegionOps sp804_ops = {
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.read = sp804_read,
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.write = sp804_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static const VMStateDescription vmstate_sp804 = {
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.name = "sp804",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_INT32_ARRAY(level, SP804State, 2),
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VMSTATE_END_OF_LIST()
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}
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};
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static void sp804_init(Object *obj)
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{
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SP804State *s = SP804(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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sysbus_init_irq(sbd, &s->irq);
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memory_region_init_io(&s->iomem, obj, &sp804_ops, s,
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"sp804", 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static void sp804_realize(DeviceState *dev, Error **errp)
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{
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SP804State *s = SP804(dev);
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s->timer[0] = arm_timer_init(s->freq0);
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s->timer[1] = arm_timer_init(s->freq1);
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s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0);
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s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1);
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}
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/* Integrator/CP timer module. */
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#define TYPE_INTEGRATOR_PIT "integrator_pit"
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OBJECT_DECLARE_SIMPLE_TYPE(icp_pit_state, INTEGRATOR_PIT)
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struct icp_pit_state {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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arm_timer_state *timer[3];
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};
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static uint64_t icp_pit_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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icp_pit_state *s = (icp_pit_state *)opaque;
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int n;
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/* ??? Don't know the PrimeCell ID for this device. */
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n = offset >> 8;
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if (n > 2) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
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return 0;
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}
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return arm_timer_read(s->timer[n], offset & 0xff);
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}
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static void icp_pit_write(void *opaque, hwaddr offset,
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uint64_t value, unsigned size)
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{
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icp_pit_state *s = (icp_pit_state *)opaque;
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int n;
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n = offset >> 8;
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if (n > 2) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n);
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return;
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}
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arm_timer_write(s->timer[n], offset & 0xff, value);
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}
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static const MemoryRegionOps icp_pit_ops = {
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.read = icp_pit_read,
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.write = icp_pit_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void icp_pit_init(Object *obj)
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{
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icp_pit_state *s = INTEGRATOR_PIT(obj);
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SysBusDevice *dev = SYS_BUS_DEVICE(obj);
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/* Timer 0 runs at the system clock speed (40MHz). */
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s->timer[0] = arm_timer_init(40000000);
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/* The other two timers run at 1MHz. */
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s->timer[1] = arm_timer_init(1000000);
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s->timer[2] = arm_timer_init(1000000);
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sysbus_init_irq(dev, &s->timer[0]->irq);
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sysbus_init_irq(dev, &s->timer[1]->irq);
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sysbus_init_irq(dev, &s->timer[2]->irq);
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memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s,
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"icp_pit", 0x1000);
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sysbus_init_mmio(dev, &s->iomem);
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/* This device has no state to save/restore. The component timers will
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save themselves. */
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}
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static const TypeInfo icp_pit_info = {
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.name = TYPE_INTEGRATOR_PIT,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(icp_pit_state),
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.instance_init = icp_pit_init,
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};
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static Property sp804_properties[] = {
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DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000),
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DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void sp804_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *k = DEVICE_CLASS(klass);
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k->realize = sp804_realize;
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device_class_set_props(k, sp804_properties);
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k->vmsd = &vmstate_sp804;
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}
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static const TypeInfo sp804_info = {
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.name = TYPE_SP804,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(SP804State),
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.instance_init = sp804_init,
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.class_init = sp804_class_init,
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};
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static void arm_timer_register_types(void)
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{
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type_register_static(&icp_pit_info);
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type_register_static(&sp804_info);
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}
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type_init(arm_timer_register_types)
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