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![Ben Widawsky](/assets/img/avatar_default.png)
This adds just enough of a root port implementation to be able to enumerate root ports (creating the required DVSEC entries). What's not here yet is the MMIO nor the ability to write some of the DVSEC entries. This can be added with the qemu commandline by adding a rootport to a specific CXL host bridge. For example: -device cxl-rp,id=rp0,bus="cxl.0",addr=0.0,chassis=4 Like the host bridge patch, the ACPI tables aren't generated at this point and so system software cannot use it. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20220429144110.25167-17-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
203 lines
5 KiB
C
203 lines
5 KiB
C
/*
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* Base class for PCI Express Root Ports
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*
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* Copyright (C) 2017 Red Hat Inc
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*
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* Authors:
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* Marcel Apfelbaum <marcel@redhat.com>
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*
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* Most of the code was migrated from hw/pci-bridge/ioh3420.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/pci/pcie_port.h"
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#include "hw/qdev-properties.h"
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static void rp_aer_vector_update(PCIDevice *d)
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{
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
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if (rpc->aer_vector) {
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pcie_aer_root_set_vector(d, rpc->aer_vector(d));
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}
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}
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static void rp_write_config(PCIDevice *d, uint32_t address,
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uint32_t val, int len)
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{
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uint32_t root_cmd =
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pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
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uint16_t slt_ctl, slt_sta;
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pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
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pci_bridge_write_config(d, address, val, len);
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rp_aer_vector_update(d);
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pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
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pcie_aer_write_config(d, address, val, len);
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pcie_aer_root_write_config(d, address, val, len, root_cmd);
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}
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static void rp_reset(DeviceState *qdev)
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{
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PCIDevice *d = PCI_DEVICE(qdev);
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rp_aer_vector_update(d);
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pcie_cap_root_reset(d);
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pcie_cap_deverr_reset(d);
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pcie_cap_slot_reset(d);
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pcie_cap_arifwd_reset(d);
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pcie_acs_reset(d);
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pcie_aer_root_reset(d);
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pci_bridge_reset(qdev);
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pci_bridge_disable_base_limit(d);
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}
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static void rp_realize(PCIDevice *d, Error **errp)
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{
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PCIEPort *p = PCIE_PORT(d);
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PCIESlot *s = PCIE_SLOT(d);
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PCIDeviceClass *dc = PCI_DEVICE_GET_CLASS(d);
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
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int rc;
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pci_config_set_interrupt_pin(d->config, 1);
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if (d->cap_present & QEMU_PCIE_CAP_CXL) {
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pci_bridge_initfn(d, TYPE_CXL_BUS);
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} else {
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pci_bridge_initfn(d, TYPE_PCIE_BUS);
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}
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pcie_port_init_reg(d);
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rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id,
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rpc->ssid, errp);
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if (rc < 0) {
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error_append_hint(errp, "Can't init SSV ID, error %d\n", rc);
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goto err_bridge;
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}
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if (rpc->interrupts_init) {
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rc = rpc->interrupts_init(d, errp);
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if (rc < 0) {
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goto err_bridge;
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}
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}
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rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT,
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p->port, errp);
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if (rc < 0) {
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error_append_hint(errp, "Can't add Root Port capability, "
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"error %d\n", rc);
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goto err_int;
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}
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pcie_cap_arifwd_init(d);
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pcie_cap_deverr_init(d);
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pcie_cap_slot_init(d, s);
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pcie_cap_root_init(d);
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pcie_chassis_create(s->chassis);
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rc = pcie_chassis_add_slot(s);
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if (rc < 0) {
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error_setg(errp, "Can't add chassis slot, error %d", rc);
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goto err_pcie_cap;
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}
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rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset,
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PCI_ERR_SIZEOF, errp);
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if (rc < 0) {
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goto err;
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}
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pcie_aer_root_init(d);
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rp_aer_vector_update(d);
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if (rpc->acs_offset && !s->disable_acs) {
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pcie_acs_init(d, rpc->acs_offset);
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}
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return;
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err:
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pcie_chassis_del_slot(s);
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err_pcie_cap:
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pcie_cap_exit(d);
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err_int:
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if (rpc->interrupts_uninit) {
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rpc->interrupts_uninit(d);
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}
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err_bridge:
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pci_bridge_exitfn(d);
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}
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static void rp_exit(PCIDevice *d)
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{
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PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
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PCIESlot *s = PCIE_SLOT(d);
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pcie_aer_exit(d);
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pcie_chassis_del_slot(s);
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pcie_cap_exit(d);
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if (rpc->interrupts_uninit) {
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rpc->interrupts_uninit(d);
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}
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pci_bridge_exitfn(d);
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}
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static Property rp_props[] = {
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DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
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QEMU_PCIE_SLTCAP_PCP_BITNR, true),
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DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false),
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DEFINE_PROP_END_OF_LIST()
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};
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static void rp_instance_post_init(Object *obj)
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{
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PCIESlot *s = PCIE_SLOT(obj);
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if (!s->speed) {
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s->speed = QEMU_PCI_EXP_LNK_2_5GT;
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}
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if (!s->width) {
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s->width = QEMU_PCI_EXP_LNK_X1;
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}
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}
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static void rp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->is_bridge = true;
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k->config_write = rp_write_config;
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k->realize = rp_realize;
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k->exit = rp_exit;
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set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
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dc->reset = rp_reset;
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device_class_set_props(dc, rp_props);
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}
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static const TypeInfo rp_info = {
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.name = TYPE_PCIE_ROOT_PORT,
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.parent = TYPE_PCIE_SLOT,
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.instance_post_init = rp_instance_post_init,
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.class_init = rp_class_init,
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.abstract = true,
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.class_size = sizeof(PCIERootPortClass),
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_PCIE_DEVICE },
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{ }
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},
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};
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static void rp_register_types(void)
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{
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type_register_static(&rp_info);
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}
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type_init(rp_register_types)
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