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![Joel Stanley](/assets/img/avatar_default.png)
In order to correctly report secure boot running firmware the values of certain registers must be set. We don't yet have documentation from ASPEED on what they mean. The meaning is inferred from u-boot's use of them. Introduce properties so the settings can be configured per-machine. Reviewed-by: Peter Delevoryas <pdel@fb.com> Tested-by: Peter Delevoryas <pdel@fb.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20220628154740.1117349-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
183 lines
4.7 KiB
C
183 lines
4.7 KiB
C
/*
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* ASPEED Secure Boot Controller
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*
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* Copyright (C) 2021-2022 IBM Corp.
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*
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* Joel Stanley <joel@jms.id.au>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/error-report.h"
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#include "hw/qdev-properties.h"
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#include "hw/misc/aspeed_sbc.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#define R_PROT (0x000 / 4)
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#define R_STATUS (0x014 / 4)
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#define R_QSR (0x040 / 4)
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/* R_STATUS */
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#define ABR_EN BIT(14) /* Mirrors SCU510[11] */
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#define ABR_IMAGE_SOURCE BIT(13)
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#define SPI_ABR_IMAGE_SOURCE BIT(12)
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#define SB_CRYPTO_KEY_EXP_DONE BIT(11)
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#define SB_CRYPTO_BUSY BIT(10)
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#define OTP_WP_EN BIT(9)
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#define OTP_ADDR_WP_EN BIT(8)
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#define LOW_SEC_KEY_EN BIT(7)
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#define SECURE_BOOT_EN BIT(6)
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#define UART_BOOT_EN BIT(5)
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/* bit 4 reserved*/
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#define OTP_CHARGE_PUMP_READY BIT(3)
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#define OTP_IDLE BIT(2)
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#define OTP_MEM_IDLE BIT(1)
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#define OTP_COMPARE_STATUS BIT(0)
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/* QSR */
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#define QSR_RSA_MASK (0x3 << 12)
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#define QSR_HASH_MASK (0x3 << 10)
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static uint64_t aspeed_sbc_read(void *opaque, hwaddr addr, unsigned int size)
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{
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AspeedSBCState *s = ASPEED_SBC(opaque);
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addr >>= 2;
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if (addr >= ASPEED_SBC_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr << 2);
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return 0;
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}
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return s->regs[addr];
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}
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static void aspeed_sbc_write(void *opaque, hwaddr addr, uint64_t data,
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unsigned int size)
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{
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AspeedSBCState *s = ASPEED_SBC(opaque);
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addr >>= 2;
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if (addr >= ASPEED_SBC_NR_REGS) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
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__func__, addr << 2);
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return;
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}
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switch (addr) {
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case R_STATUS:
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case R_QSR:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: write to read only register 0x%" HWADDR_PRIx "\n",
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__func__, addr << 2);
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return;
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default:
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break;
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}
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s->regs[addr] = data;
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}
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static const MemoryRegionOps aspeed_sbc_ops = {
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.read = aspeed_sbc_read,
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.write = aspeed_sbc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4,
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},
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};
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static void aspeed_sbc_reset(DeviceState *dev)
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{
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struct AspeedSBCState *s = ASPEED_SBC(dev);
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memset(s->regs, 0, sizeof(s->regs));
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/* Set secure boot enabled with RSA4096_SHA256 and enable eMMC ABR */
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s->regs[R_STATUS] = OTP_IDLE | OTP_MEM_IDLE;
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if (s->emmc_abr) {
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s->regs[R_STATUS] &= ABR_EN;
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}
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if (s->signing_settings) {
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s->regs[R_STATUS] &= SECURE_BOOT_EN;
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}
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s->regs[R_QSR] = s->signing_settings;
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}
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static void aspeed_sbc_realize(DeviceState *dev, Error **errp)
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{
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AspeedSBCState *s = ASPEED_SBC(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sbc_ops, s,
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TYPE_ASPEED_SBC, 0x1000);
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sysbus_init_mmio(sbd, &s->iomem);
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}
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static const VMStateDescription vmstate_aspeed_sbc = {
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.name = TYPE_ASPEED_SBC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, AspeedSBCState, ASPEED_SBC_NR_REGS),
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VMSTATE_END_OF_LIST(),
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}
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};
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static Property aspeed_sbc_properties[] = {
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DEFINE_PROP_BOOL("emmc-abr", AspeedSBCState, emmc_abr, 0),
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DEFINE_PROP_UINT32("signing-settings", AspeedSBCState, signing_settings, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void aspeed_sbc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = aspeed_sbc_realize;
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dc->reset = aspeed_sbc_reset;
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dc->vmsd = &vmstate_aspeed_sbc;
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device_class_set_props(dc, aspeed_sbc_properties);
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}
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static const TypeInfo aspeed_sbc_info = {
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.name = TYPE_ASPEED_SBC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AspeedSBCState),
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.class_init = aspeed_sbc_class_init,
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.class_size = sizeof(AspeedSBCClass)
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};
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static void aspeed_ast2600_sbc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->desc = "AST2600 Secure Boot Controller";
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}
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static const TypeInfo aspeed_ast2600_sbc_info = {
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.name = TYPE_ASPEED_AST2600_SBC,
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.parent = TYPE_ASPEED_SBC,
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.class_init = aspeed_ast2600_sbc_class_init,
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};
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static void aspeed_sbc_register_types(void)
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{
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type_register_static(&aspeed_ast2600_sbc_info);
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type_register_static(&aspeed_sbc_info);
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}
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type_init(aspeed_sbc_register_types);
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