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![Philippe Mathieu-Daudé](/assets/img/avatar_default.png)
- Embed SerialMM in MchpPfSoCMMUartState and QOM-initialize it - Alias SERIAL_MM 'chardev' property on MCHP_PFSOC_UART - Forward SerialMM sysbus IRQ in mchp_pfsoc_mmuart_realize() - Add DeviceReset() method - Add vmstate structure for migration - Register device in 'input' category - Keep mchp_pfsoc_mmuart_create() behavior Note, serial_mm_init() calls qdev_set_legacy_instance_id(). This call is only needed for backwards-compatibility of incoming migration data with old versions of QEMU which implemented migration of devices with hand-rolled code. Since this device didn't previously handle migration at all, then it doesn't need to set the legacy instance ID. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210925133407.1259392-4-f4bug@amsat.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
164 lines
5 KiB
C
164 lines
5 KiB
C
/*
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* Microchip PolarFire SoC MMUART emulation
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*
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* Copyright (c) 2020 Wind River Systems, Inc.
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*
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* Author:
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* Bin Meng <bin.meng@windriver.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 or
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* (at your option) version 3 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "hw/char/mchp_pfsoc_mmuart.h"
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#include "hw/qdev-properties.h"
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#define REGS_OFFSET 0x20
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static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size)
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{
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MchpPfSoCMMUartState *s = opaque;
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addr >>= 2;
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if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n",
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__func__, addr << 2);
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return 0;
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}
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return s->reg[addr];
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}
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static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned size)
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{
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MchpPfSoCMMUartState *s = opaque;
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uint32_t val32 = (uint32_t)value;
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addr >>= 2;
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if (addr >= MCHP_PFSOC_MMUART_REG_COUNT) {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx
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" v=0x%x\n", __func__, addr << 2, val32);
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return;
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}
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s->reg[addr] = val32;
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}
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static const MemoryRegionOps mchp_pfsoc_mmuart_ops = {
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.read = mchp_pfsoc_mmuart_read,
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.write = mchp_pfsoc_mmuart_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void mchp_pfsoc_mmuart_reset(DeviceState *dev)
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{
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MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
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memset(s->reg, 0, sizeof(s->reg));
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device_cold_reset(DEVICE(&s->serial_mm));
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}
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static void mchp_pfsoc_mmuart_init(Object *obj)
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{
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MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(obj);
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object_initialize_child(obj, "serial-mm", &s->serial_mm, TYPE_SERIAL_MM);
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object_property_add_alias(obj, "chardev", OBJECT(&s->serial_mm), "chardev");
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}
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static void mchp_pfsoc_mmuart_realize(DeviceState *dev, Error **errp)
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{
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MchpPfSoCMMUartState *s = MCHP_PFSOC_UART(dev);
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qdev_prop_set_uint8(DEVICE(&s->serial_mm), "regshift", 2);
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qdev_prop_set_uint32(DEVICE(&s->serial_mm), "baudbase", 399193);
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qdev_prop_set_uint8(DEVICE(&s->serial_mm), "endianness",
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DEVICE_LITTLE_ENDIAN);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->serial_mm), errp)) {
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return;
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}
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sysbus_pass_irq(SYS_BUS_DEVICE(dev), SYS_BUS_DEVICE(&s->serial_mm));
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memory_region_init(&s->container, OBJECT(s), "mchp.pfsoc.mmuart", 0x1000);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
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memory_region_add_subregion(&s->container, 0,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->serial_mm), 0));
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memory_region_init_io(&s->iomem, OBJECT(s), &mchp_pfsoc_mmuart_ops, s,
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"mchp.pfsoc.mmuart.regs", 0x1000 - REGS_OFFSET);
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memory_region_add_subregion(&s->container, REGS_OFFSET, &s->iomem);
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}
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static const VMStateDescription mchp_pfsoc_mmuart_vmstate = {
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.name = "mchp.pfsoc.uart",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(reg, MchpPfSoCMMUartState,
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MCHP_PFSOC_MMUART_REG_COUNT),
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VMSTATE_END_OF_LIST()
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}
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};
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static void mchp_pfsoc_mmuart_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = mchp_pfsoc_mmuart_realize;
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dc->reset = mchp_pfsoc_mmuart_reset;
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dc->vmsd = &mchp_pfsoc_mmuart_vmstate;
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set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
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}
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static const TypeInfo mchp_pfsoc_mmuart_info = {
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.name = TYPE_MCHP_PFSOC_UART,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(MchpPfSoCMMUartState),
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.instance_init = mchp_pfsoc_mmuart_init,
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.class_init = mchp_pfsoc_mmuart_class_init,
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};
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static void mchp_pfsoc_mmuart_register_types(void)
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{
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type_register_static(&mchp_pfsoc_mmuart_info);
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}
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type_init(mchp_pfsoc_mmuart_register_types)
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MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem,
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hwaddr base,
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qemu_irq irq, Chardev *chr)
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{
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DeviceState *dev = qdev_new(TYPE_MCHP_PFSOC_UART);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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qdev_prop_set_chr(dev, "chardev", chr);
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sysbus_realize(sbd, &error_fatal);
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memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(sbd, 0));
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sysbus_connect_irq(sbd, 0, irq);
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return MCHP_PFSOC_UART(dev);
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}
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