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https://gitlab.com/qemu-project/qemu
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99f4ec6eab
Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
22 lines
479 B
C
22 lines
479 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define RISC-V target-specific operand constraints.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('I', TCG_CT_CONST_S12)
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CONST('J', TCG_CT_CONST_J12)
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CONST('N', TCG_CT_CONST_N12)
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CONST('M', TCG_CT_CONST_M12)
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CONST('Z', TCG_CT_CONST_ZERO)
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