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Lower the following ops: - add_vec - sub_vec Signed-off-by: Jiajie Chen <c@jia.je> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230908022302.180442-6-c@jia.je> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
31 lines
701 B
C
31 lines
701 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define LoongArch target-specific operand constraints.
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*
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* Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
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*
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* Based on tcg/riscv/tcg-target-con-str.h
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*
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('w', ALL_VECTOR_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('I', TCG_CT_CONST_S12)
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CONST('J', TCG_CT_CONST_S32)
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CONST('U', TCG_CT_CONST_U12)
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CONST('Z', TCG_CT_CONST_ZERO)
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CONST('C', TCG_CT_CONST_C12)
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CONST('W', TCG_CT_CONST_WSZ)
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CONST('M', TCG_CT_CONST_VCMP)
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CONST('A', TCG_CT_CONST_VADD)
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