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6bfcf1dc23
Add support for the clrbhrb and mfbhrbe instructions. Since neither instruction is believed to be critical to performance, both instructions were implemented using helper functions. Access to both instructions is controlled by bits in the HFSCR (for privileged state) and MMCR0 (for problem state). A new function, helper_mmcr0_facility_check, was added for checking MMCR0[BHRBA] and raising a facility_unavailable exception if required. NOTE: For P8 and P9, due to a performance issue, branch history will not be kept, but the instructions will be allowed to execute as normal with the exception that the mfbhrbe instruction will always return a zero value. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
44 lines
958 B
C++
44 lines
958 B
C++
/*
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* Power ISA Decode For BHRB Instructions
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*
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* Copyright IBM Corp. 2023
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*
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* Authors:
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* Glenn Miles <milesg@linux.vnet.ibm.com>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
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static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg)
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{
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REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
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TCGv_i32 bhrbe = tcg_constant_i32(arg->bhrbe);
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gen_helper_mfbhrbe(cpu_gpr[arg->rt], tcg_env, bhrbe);
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return true;
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}
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static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg)
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{
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REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
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gen_helper_clrbhrb(tcg_env);
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return true;
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}
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#else
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static bool trans_MFBHRBE(DisasContext *ctx, arg_XFX_bhrbe *arg)
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{
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gen_invalid(ctx);
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return true;
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}
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static bool trans_CLRBHRB(DisasContext *ctx, arg_CLRBHRB *arg)
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{
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gen_invalid(ctx);
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return true;
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}
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#endif
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