mirror of
https://gitlab.com/qemu-project/qemu
synced 2024-11-05 20:35:44 +00:00
43ac657423
M profile doesn't have the MSR(banked) and MRS(banked) instructions and uses the encodings for different kinds of M-profile MRS/MSR. Guard the relevant bits of the decode logic to make sure we don't accidentally fall into them by accident on M-profile. (The bit being checked for this (bit 5) is part of the SYSm field on M-profile, but since no currently allocated system registers have encodings with bit 5 of SYSm set, this hasn't been a problem in practice.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487616072-9226-3-git-send-email-peter.maydell@linaro.org |
||
---|---|---|
.. | ||
alpha | ||
arm | ||
cris | ||
hppa | ||
i386 | ||
lm32 | ||
m68k | ||
microblaze | ||
mips | ||
moxie | ||
nios2 | ||
openrisc | ||
ppc | ||
s390x | ||
sh4 | ||
sparc | ||
tilegx | ||
tricore | ||
unicore32 | ||
xtensa |