mirror of
https://gitlab.com/qemu-project/qemu
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e2bed107c6
Add instructions of RR opcode format, that have 0x4b as the first opcode.
Add helper functions:
* parity: Calculates the parity bits for every byte of a 32 int.
* bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two bitwise.
* unpack: unpack a IEEE 754 single precision floating point number as exponent and mantissa.
* dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
where the quotient result is guaranteed to fit into 8 bit.
* dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation,
where the quotient result is guaranteed to fit into 16 bit.
OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE.
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
105 lines
4.5 KiB
C
105 lines
4.5 KiB
C
/*
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* Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* Arithmetic */
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DEF_HELPER_3(add_ssov, i32, env, i32, i32)
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DEF_HELPER_3(add_suov, i32, env, i32, i32)
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DEF_HELPER_3(add_h_ssov, i32, env, i32, i32)
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DEF_HELPER_3(add_h_suov, i32, env, i32, i32)
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DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
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DEF_HELPER_3(sub_suov, i32, env, i32, i32)
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DEF_HELPER_3(sub_h_ssov, i32, env, i32, i32)
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DEF_HELPER_3(sub_h_suov, i32, env, i32, i32)
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DEF_HELPER_3(mul_ssov, i32, env, i32, i32)
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DEF_HELPER_3(mul_suov, i32, env, i32, i32)
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DEF_HELPER_3(sha_ssov, i32, env, i32, i32)
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DEF_HELPER_3(absdif_ssov, i32, env, i32, i32)
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DEF_HELPER_4(madd32_ssov, i32, env, i32, i32, i32)
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DEF_HELPER_4(madd32_suov, i32, env, i32, i32, i32)
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DEF_HELPER_4(madd64_ssov, i64, env, i32, i64, i32)
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DEF_HELPER_4(madd64_suov, i64, env, i32, i64, i32)
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DEF_HELPER_4(msub32_ssov, i32, env, i32, i32, i32)
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DEF_HELPER_4(msub32_suov, i32, env, i32, i32, i32)
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DEF_HELPER_4(msub64_ssov, i64, env, i32, i64, i32)
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DEF_HELPER_4(msub64_suov, i64, env, i32, i64, i32)
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DEF_HELPER_3(absdif_h_ssov, i32, env, i32, i32)
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DEF_HELPER_2(abs_ssov, i32, env, i32)
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DEF_HELPER_2(abs_h_ssov, i32, env, i32)
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/* hword/byte arithmetic */
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DEF_HELPER_2(abs_b, i32, env, i32)
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DEF_HELPER_2(abs_h, i32, env, i32)
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DEF_HELPER_3(absdif_b, i32, env, i32, i32)
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DEF_HELPER_3(absdif_h, i32, env, i32, i32)
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DEF_HELPER_3(add_b, i32, env, i32, i32)
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DEF_HELPER_3(add_h, i32, env, i32, i32)
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DEF_HELPER_3(sub_b, i32, env, i32, i32)
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DEF_HELPER_3(sub_h, i32, env, i32, i32)
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DEF_HELPER_FLAGS_2(eq_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(eq_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(eqany_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(eqany_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(lt_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(lt_bu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(lt_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(lt_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(max_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(max_bu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(max_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(max_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(min_b, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(min_bu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(min_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(min_hu, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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/* count leading ... */
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DEF_HELPER_FLAGS_1(clo, TCG_CALL_NO_RWG_SE, i32, i32)
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DEF_HELPER_FLAGS_1(clo_h, TCG_CALL_NO_RWG_SE, i32, i32)
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DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, i32, i32)
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DEF_HELPER_FLAGS_1(clz_h, TCG_CALL_NO_RWG_SE, i32, i32)
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DEF_HELPER_FLAGS_1(cls, TCG_CALL_NO_RWG_SE, i32, i32)
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DEF_HELPER_FLAGS_1(cls_h, TCG_CALL_NO_RWG_SE, i32, i32)
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/* sh */
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DEF_HELPER_FLAGS_2(sh, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_2(sh_h, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_3(sha, i32, env, i32, i32)
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DEF_HELPER_2(sha_h, i32, i32, i32)
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/* merge/split/parity */
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DEF_HELPER_FLAGS_2(bmerge, TCG_CALL_NO_RWG_SE, i32, i32, i32)
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DEF_HELPER_FLAGS_1(bsplit, TCG_CALL_NO_RWG_SE, i64, i32)
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DEF_HELPER_FLAGS_1(parity, TCG_CALL_NO_RWG_SE, i32, i32)
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/* float */
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DEF_HELPER_1(unpack, i64, i32)
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/* dvinit */
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DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32)
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DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32)
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DEF_HELPER_3(dvinit_h_13, i64, env, i32, i32)
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DEF_HELPER_3(dvinit_h_131, i64, env, i32, i32)
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/* CSA */
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DEF_HELPER_2(call, void, env, i32)
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DEF_HELPER_1(ret, void, env)
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DEF_HELPER_2(bisr, void, env, i32)
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DEF_HELPER_1(rfe, void, env)
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DEF_HELPER_2(ldlcx, void, env, i32)
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DEF_HELPER_2(lducx, void, env, i32)
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DEF_HELPER_2(stlcx, void, env, i32)
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DEF_HELPER_2(stucx, void, env, i32)
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/* Address mode helper */
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DEF_HELPER_1(br_update, i32, i32)
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DEF_HELPER_2(circ_update, i32, i32, i32)
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/* PSW cache helper */
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DEF_HELPER_2(psw_write, void, env, i32)
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DEF_HELPER_1(psw_read, i32, env)
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