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https://gitlab.com/qemu-project/qemu
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339adf2f38
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
25 lines
583 B
C
25 lines
583 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Define AArch64 target-specific operand constraints.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('r', ALL_GENERAL_REGS)
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REGS('w', ALL_VECTOR_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('A', TCG_CT_CONST_AIMM)
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CONST('C', TCG_CT_CONST_CMP)
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CONST('L', TCG_CT_CONST_LIMM)
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CONST('M', TCG_CT_CONST_MONE)
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CONST('O', TCG_CT_CONST_ORRI)
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CONST('N', TCG_CT_CONST_ANDI)
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CONST('Z', TCG_CT_CONST_ZERO)
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