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Support for emulating XThead* instruction has been added recently. This patch adds support for these instructions to the RISC-V disassembler. Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
29 lines
818 B
C
29 lines
818 B
C
/*
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* QEMU disassembler -- RISC-V specific header (xthead*).
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*
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* Copyright (c) 2023 VRULL GmbH
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef DISAS_RISCV_XTHEAD_H
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#define DISAS_RISCV_XTHEAD_H
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#include "disas/riscv.h"
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extern const rv_opcode_data xthead_opcode_data[];
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void decode_xtheadba(rv_decode *, rv_isa);
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void decode_xtheadbb(rv_decode *, rv_isa);
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void decode_xtheadbs(rv_decode *, rv_isa);
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void decode_xtheadcmo(rv_decode *, rv_isa);
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void decode_xtheadcondmov(rv_decode *, rv_isa);
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void decode_xtheadfmemidx(rv_decode *, rv_isa);
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void decode_xtheadfmv(rv_decode *, rv_isa);
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void decode_xtheadmac(rv_decode *, rv_isa);
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void decode_xtheadmemidx(rv_decode *, rv_isa);
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void decode_xtheadmempair(rv_decode *, rv_isa);
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void decode_xtheadsync(rv_decode *, rv_isa);
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#endif /* DISAS_RISCV_XTHEAD_H */
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